ADN2860 查看數據表（PDF） - Analog Devices
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ADN2860 Datasheet PDF : 20 Pages
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ADN2860
A random read operation is shown in Figure 21. This operation
changes the address counter to the specified memory address by
performing a dummy write and then performing a read
operation beginning at the new address counter location.
EEPROM Write Protection
Setting the WP pin to logic low protects the EEPROM memory
from future write operations. In this mode, EEPROM read
operations and RDAC register loading operate normally.
RDAC I2C INTERFACE
S 0 1 0 1 1 A A 0 A CMD/ 0
EE/
AAAA AA
10
REG
RD
4321 0
RR
AC
RDAC SLAVE ADDRESS
0 WRITE
RDAC ADDRESS
Figure 22. RDAC Write
DATA
A
DATA
A/A P
(N BYTES + ACKNOWLEDGE)
S0 1 0 1 1 AA1A
10
RR
RDAC SLAVE ADDRESS
1 READ
RDAC EEPROM OR REGISTER DATA
A
RDAC EEPROM OR REGISTER DATA
(N BYTES + ACKNOWLEDGE)
Figure 23. RDAC Current Read
AP
S
SLAVE ADDRESS
W
A
RDAC ADDRESS
A
S
SLAVE ADDRESS
R
A
RDAC DATA
A/A
P
0 WRITE
REPEATED START
Figure 24. RDAC Random Read
1 READ
(N BYTES + ACKNOWLEDGE)
S
0
1
0
1
1
A
A0
A CMD/
CC
CCAAA
AP
1
0
REG
3
2
1
0
2
1
0
RR
RDAC SLAVE ADDRESS
0 WRITE
1 CMD
Figure 25. RDAC Shortcut Commands
Table 5. RDAC Register Addresses (CMD/REG = 0, EE/RDAC = 0)
A4 A3 A2 A1 A0
RDAC
Byte Description
0
0
0
0
0
RDAC0
(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0)—RDAC0 8 LSBs
0
0
0
0
1
RDAC0
(X)(X)(X)(X)(X)(X)(X)(D8)—RDAC0 MSB
0
0
0
1
0
RDAC1
(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0)—RDAC1 8 LSBs
0
0
0
1
1
RDAC1
(X)(X)(X)(X)(X)(X)(X)(D8)—RDAC1 MSB
0
0
1
0
0
RDAC2
(X)(D6)(D5)(D4)(D3)(D2)(D1)(D0)—RDAC2 7 bits
0
0
1
0
1
Reserved
…to…
1
1
1
1
1
Rev. A | Page 12 of 20
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