ADP3041 查看數據表（PDF） - Analog Devices

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ADP3041

TFT LCD Panel Power Module

Analog Devices 

ADP3041

ERROR

AMP

REF

COMP

gm

FB

RC

C2

CC

Figure 2. Compensation Components

The boost regulator introduces a right half plane (RHP) zero. This

zero behaves like a zero with respect to the gain but behaves

like a pole with respect to phase. As a result, the RHP zero can

cause instability of the control loop if the bandwidth (in Hertz)

of the loop includes it.

( ) fZ RHP

=





VIN

VOUT

2



×

RLOAD

2π × L

(8)

Note that the RHP zero is dependant on the load. To optimize

the compensation, a nominal load must be chosen. Typically,

choosing an RLOAD that is halfway between no load and full

load works well; but make sure that this load is enough to ensure

CCM operation. The critical value of load resistance, RCRIT, for

CCM is given by

RCRIT

=

2 × L × fSW



1

–

VIN

VOUT









VIN

VOUT

2



(9)

So for the nominal load resistance RLOAD, use the half load

resistance or RCRIT, whichever is lower.

To make sure the RHP zero does not cause stability problems,

the control loop bandwidth should be set at around 1/8 the

frequency (in Hertz) of the RHP zero.

fC

=

1

8

×

fZ (RHP)

(10)

where fC is the crossover frequency.

Another frequency of interest is the pole caused by the output

load and output capacitor. This frequency (in Hertz) is calcu-

lated using

fP1

=

1

2π × RLOAD

× COUT

(11)

Note that the frequency varies with load current. Again, use the

nominal load resistance for the calculation.

So the compensation resistor, RC, can be calculated by deter-

mining the open-loop gain at the crossover frequency, fC, and

setting RC to adjust the closed-loop gain to zero. The open-loop

gain can be approximated (in dB) by

( ) GOC

fC

=

20



log

VIN ×

VOUT

RLOAD

× 0.65





–



20 log 



1+





fC

fP1





2







(12)

RC

=

gm

1

× VFB

GOC ( f C )

× 10 20

VOUT

(13)

Once the value of the compensation resistor is determined, the

value of the compensation capacitor, CC, can be calculated. The

compensation capacitor sets up a zero to cancel out the pole

created by the output load, fP1. Since the load pole position

varies with load current, the compensation zero should be located

approximately four times the worst-case load pole, 4 × fP1, or at

one half the crossover frequency, 1/2 × fC, whichever is lower.

The frequency of the compensation zero is located at

fZC

=

1

2 × π × RC

× CC

(14)

So, the value of CC can be calculated using

CC

=

2×π×

1

fZC

× RC

(15)

If the output capacitor selected has a high ESR value, it may be

necessary to add another pole to cancel the zero introduced by

the capacitor’s ESR. The ESR zero location is determined by

( ) fZ

ESR

=

1

2 × π × RESR × COUT

(16)

So, a high frequency pole should be placed to cancel the ESR

zero or at half the switching frequency, whichever is lower. By

placing a pole at half the switching frequency, the high fre-

quency gain is rolled off for better phase margin. Note that the

high frequency pole must be at least a decade above the com-

pensation zero in order for the compensation to work properly.

If this is not the case, the high frequency pole should not be used.

( ) C2 =

CC

1 + 2π × fP(HF ) × RC × CC

(17)

After all the compensation components have been selected, the

best check for stability and response time is to observe the tran-

sient performance of the ADP3041. Adjust RC and CC as necessary

to optimize the transient response. Increasing RC increases

REV. D

–13–

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