ADP3810AR-126 查看數據表（PDF） - Analog Devices
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ADP3810AR-126 Datasheet PDF : 16 Pages
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ADP3810/ADP3811
either present or absent. If the battery is present, its large ca-
pacitance creates a very low frequency dominant pole, giving a
single pole system. The more demanding case is when the bat-
tery is removed. Now the output pole is dependent upon the
filter capacitors, CF1 and CF2. This pole is higher in frequency,
and more care must be taken to stabilize the loop response. All
three cases are described in detail below.
The following calculations for compensation components help
to realize stable voltage and current loops. In practical designs,
checking the stability using a network analyzer or a Feedback
Loop Analyzer is always recommended. The calculated compo-
nent values serve as good starting values for a measurement-
based optimization. The component values shown in Figure 23
are slightly different from the calculated values based on this
optimization procedure.
To simplify the analysis further, the loop gain is split into two
components: the gain from the battery to the ADP3810/
ADP3811’s COMP pin and the gain from the COMP pin back
to the battery. Because the compensation of each loop depends
upon the RC network on the COMP pin, it is a convenient
choice for dividing the loop calculations.
Definitions:
Modulator Gain: GMOD = gain in dB from the COMP pin to
VBAT.
Error Amplifier: GEA = gain in dB from VBAT to the COMP pin.
Loop Gain:
GLOOP = GMOD + GEA.
Modulator Pole: fPM, The pole present at the output of the
modulator.
Modulator Zero: fZM, The zero due to the ESR, RF1, of the
filter cap, CF1.
Voltage Loop Compensation, No Battery
Step 1. Calculate the dc loop gain (GLOOP), fPM, and fZM:
[ ] GMOD = 20 × log GM 3 × ITXOC × RF × AV 2 ×GM 4 × R4
6 mA / V × 0.36 × 3.3 kΩ ×
GMOD = 20 × log
= 48.3 dB
0.333 × 0.091 A / V × 1.2 kΩ
G EA
=
20
×
log
R2
R1+ R2
×
GM
2
×
R5
G EA
=
20
×
log
80
20 kΩ
kΩ + 20
kΩ
× 2.1mA /V
× 400 kΩ
= 48.5 dB
GLOOP = 44.5 dB + 48.3 dB = 96.8 dB
( ) ( ) fPM
=
1
2π × R4 × CF1 + CF2
=
1
2π ×1.2 kΩ × 1.22 mF
= 0.11 Hz
f
ZM
=
2π
×
1
RF1
×
C F1
=
2π
×
1
0.1 Ω × 1.0
mF
= 1.6
kHz
In reality, the interaction of CF1 and CF2 and their ESRs create
an additional pole/zero pair, but because the value of RF1 (ESR
of CF1) and RF2 (ESR of CF2) are similar, they tend to cancel
each other out. Furthermore, the loop crossover is an order of
magnitude lower in frequency, so the additional pole and zero
have little effect on the loop response.
Step 2. Pick the voltage and current loop crossover frequen-
cies, fCV and fCI:
To avoid interference between the voltage loop and the current
loop, use fCV < 1/10 of fCI, the current loop crossover. The cur-
rent loop crossover fCI is chosen to be ~ 1.9 kHz to provide a
fast current limiting response time, so pick fCV ~ 100 Hz.
Step 3. Calculate GMOD at fCV:
The modulator gain of 46.7 dB is the dc gain. The modulator
pole reduces this gain above fPM.
GMOD (100 Hz ) = GMOD (dc)− 20 × log
1+
f
f
CV
PM
2
GMOD (100 Hz ) = 48.3 dB − 20 × log
1+
100 2
0.11
=
−10.9
dB
Step 4. Calculate gain loss of GEA at fCV:
To have the feedback loop gain cross over 0 dB at fCV = 100 Hz,
GEA (100 Hz) should be +10.9 dB. Thus, the total gain loss of
GEA needed at crossover is:
GLOSS = GEA (dc) – GEA (100 Hz) = 48.5 dB – 10.9 dB = 37.6 dB
Step 5. Determine fP needed to achieve GLOSS:
To achieve this GLOSS we need to add a pole, which is located at
the COMP pin. GM2 has practically no parasitic loss in
gain at 100 Hz. Its first parasitic pole occurs at approximately
500 kHz as shown in Figure 11. Thus, the entire gain loss must
be realized with an external compensation capacitor, CC1, that
sets the pole, fP1.
f P1 =
f CV
= 1.3 Hz
GLOSS
10 10 − 1
Step 6. Calculate CC1 based upon fP:
CC1
=
2π
×
1
R5 ×
f P1
≈
0.3 µF
Step 7. Calculate the loop phase margin, ⌽M:
The loop phase margin is a combination of the phase of the
modulator pole and zero and the error amplifier pole.
ΦM
= 180 − arc tan
f CV
f P1
− arc tan
f
f
CV
PM
+ arc tan
f
f
CV
ZM
≈ 0°
Step 8. Calculate RC1 to stabilize the loop:
The sum of phase losses of the modulator and error amplifier re-
sults in a loop phase of 0°, which is unacceptable for loop stabil-
ity. To stabilize the feedback loop, we have to add a phase
boosting zero to the error amplifier by inserting a resistor (RC1)
in series with the capacitor CC1. If the desired phase margin is
φM = 60 degrees, the frequency of the zero can be calculated:
fZ1 = fCV/tan φM = 57 Hz
From this, the RC1 resistor is calculated:
RC1
=
2π
×
f
1
Z1
× CC1
≈ 10
kΩ
–14–
REV. 0
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