Preliminary
GS8170LW18/36/72C-333/300/250
Special Functions
Burst Cycles
Although ΣRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Late Write Flow Through mode,
burst read or burst write cycles may also be performed. ΣRAMs provide an on-chip burst address generator that can be utilized, if
desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to
advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the
first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
SigmaRAM Pipelined Burst Reads with Counter Wrap-around
Read
Continue
Continue
Continue
Continue
CK
External
A2
XX
XX
XX
XX
Address
I nternal
A2
A3
A0
A1
A2
Address
Counter Wraps
ADV
/E1
/W
DQ
QA2
QA3
QA0
QA1
CQ
Rev: 1.00f 6/2002
14/39
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.