GS8170LW18C-250I 查看數據表（PDF） - Giga Semiconductor

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GS8170LW18C-250I

18Mb Σ1x1 Late Write SigmaRAM™ SRAM

Giga Semiconductor 

Late Write, Flow Through Read Truth Table

Preliminary

GS8170LW18/36/72C-333/300/250

E1 E ADV W B

CK (tn) (tn) (tn) (tn) (tn)

Previous

Operation

Current Operation

DQ

(tn)

DQ

(tn+1)

0→1 X F

0

XX

X

Bank Deselect

Hi-Z

***

0→1 X X 1 X X Bank Deselect Bank Deselect (Continue)

Hi-Z

***

0→1 1 T

0

XX

X

Deselect

Hi-Z

***

0→1 X X

1

XX

Deselect

Deselect (Continue)

Hi-Z

***

Write

0→1 0 T

0

0T

X

Loads new address

***

Dn

Stores DQx if Bx = 0

Write (Abort)

0→1 0 T

0

0F

X

Loads new address

***

Hi-Z

No data stored

Write Continue

0→1 X X

1

XT

Write

Increments address by 1

Dn-1

Dn

Stores DQx if Bx = 0

Write Continue (Abort)

0→1 X X

1

XF

Write

Increments address by 1

Dn-1

Hi-Z

No data stored

0→1 0 T

0

1X

X

Read

Loads new address

Qn

***

0→1 X X

1

XX

Read

Read Continue

Increments address by 1

Qn

***

Notes:

1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.

2. If one or more Bx = 0, then B = “T” else B = “F”.

3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

4. “***” indicates that the DQ input requirement / output state are determined by the previous or next operation.

5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.

6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces

of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-

nal (base) address.

Rev: 1.00f 6/2002

19/39

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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