GS8180D18GD-200 查看數據表（PDF） - Giga Semiconductor
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GS8180D18GD-200 Datasheet PDF : 28 Pages
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GS8180D18D-250/200/167/133/100
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Load
DQ
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
JTAG TAP Instruction Set Summary
Instruction Code
Description
EXTEST
000 Places the Boundary Scan Register between TDI and TDO.
IDCODE
001 Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
010 TDO.
Forces all RAM output drivers to High-Z.
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI
101 GSI private instruction.
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
BYPASS
111 Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes
1
1, 2
1
1
1
1
1
1
Rev: 2.04 4/2005
24/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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