GS8180D18D-100 查看數據表（PDF） - Giga Semiconductor
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GS8180D18D-100 Datasheet PDF : 28 Pages
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GS8180D18D-250/200/167/133/100
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input High Voltage
1.8 V Test Port Input Low Voltage
VIHJ
0.6 * VDD
VILJ
–0.3
VDD +0.3
0.3 * VDD
V
1
V
1
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
IINHJ
IINLJ
IOLJ
VOHJ
VOLJ
–300
–1
–1
1.7
—
1
uA
2
100
uA
3
1
uA
4
—
V 5, 6
0.4
V 5, 7
Test Port Output CMOS High
VOHJC VDDQ – 100 mV
—
V 5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V 5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V > Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port Timing Diagram
TCK
TDI
TMS
TDO
Parallel SRAM input
tTKC
tTKH
tTH
tTS
tTH
tTS
tTKQ
tTH
tTS
tTKL
Rev: 2.04 4/2005
25/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology
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