ADSP-21375KSZ-ENG 查看數據表（PDF） - Analog Devices

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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

DATA MODES

The upper 32 data pins of the external memory interface are

muxed (using bits in the SYSCTL register) to support the exter-

nal memory interface data (input/output), the PDAP (input

only), and the FLAGS (input/output). Table 6 provides the pin

settings.

Table 6. Function of Data Pins

DATA PIN MODE

000

001

010

011

100

101

110

111

DATA15–8

DATA7–0

EPDATA15–0

EPDATA15–0

FLAGS15–8

EPDATA7–0

FLAGS15–0

EPDATA7–0

FLAGS7–0

Reserved

Three-state all pins

BOOT MODES

Table 7. Boot Mode Selection

BOOTCFG1–0

00

01

10

11

Booting Mode

SPI Slave Boot

SPI Master Boot

EPROM/FLASH Boot

Reserved

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 2 on Page 18.

Table 8. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0

00

01

10

11

Core to CLKIN Ratio

6:1

32:1

16:1

Reserved

ADSP-21375

Rev. PrB | Page 15 of 42 | December 2005

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