ADSP-21MOD870 查看數據表（PDF） - Analog Devices

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ADSP-21MOD870

Internet Gateway Processor

Analog Devices 

ADSP-21mod870

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

tCKI

tCKIL

tCKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

Switching Characteristics:

tCKL

tCKH

tCKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

Control Signals

38

100

ns

15

ns

15

ns

0.5 tCK – 7

ns

0.5 tCK – 7

ns

0

20

ns

Timing Requirements:

tRSP

RESET Width Low

5 tCK1

ns

tMS

Mode Setup before RESET High

2

ns

tMH

Mode Setup after RESET High

5

ns

NOTE

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

tCKI

tCKIH

CLKIN

CLKOUT

tCKIL

tCKOH

tCKH

tCKL

PF(3:0)*

RESET

tMS

tMH

tRSP

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 21. Clock Signals

REV. 0

–19–

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