ADT7475 查看數據表（PDF） - Analog Devices

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ADT7475

dBCool® Remote Thermal Monitor and Fan Controller

Analog Devices 

Single Channel ADC Conversions

Setting Bit 6 of Configuration Register 2 (0x73) places the

ADT7475 into single channel ADC conversion mode. In this

mode, the ADT7475 can be made to read a single temperature

channel only. The appropriate ADC channel is selected by

writing to Bits [7:5] of the TACH1 minimum high byte

register (0x55).

Table 10. Programming Single Channel ADC Mode

for Temperatures

Register 0x55, Bits [7:5] Channel Selected

101

Remote 1 temperature

110

Local temperature

111

Remote 2 temperature

Configuration Register 2 (0x73)

Bit 4 = 1, averaging off.

Bit 6 = 1, single channel convert mode.

TACH1 Minimum High Byte Register ( 0x55)

Bits [7:5] selects ADC channel for single channel convert mode.

Overtemperature Events

Overtemperature events on any of the temperature channels can

be detected and dealt with automatically in automatic fan speed

control mode. Register 0x6A to Register 0x6C are the THERM

temperature limit registers. When a temperature exceeds its

THERM temperature limit, all PWM outputs run at the

maximum PWM duty cycle (Register 0x38, Register 0x39, and

Register 0x3A). This effectively runs the fans at the fastest

allowed speed.

ADT7475

The fans run at this speed until the temperature drops below

THERM minus hysteresis. This can be disabled by setting the

boost bit in Configuration Register 3 (0x78), Bit 2. The

hysteresis value for the THERM temperature limit is the value

programmed into Register 0x6D and Register 0x6E (hysteresis

registers). The default hysteresis value is 4°C.

THERM LIMIT

TEMPERATURE

HYSTERESIS (°C)

FANS

100%

Figure 24. THERM Temperature Limit Operation

THERM can be disabled on specific temperature channels using

Bits [7:5] of Configuration Register 5 (0x7C). THERM can also

be disabled by:

• In Offset 64 mode, writing −64°C to the appropriate THERM

temperature limit.

• In twos complement mode, writing −128°C to the

appropriate THERM temperature limit.

Rev. A | Page 19 of 68

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