EVAL-ADT75EBZ(RevB) 查看數據表（PDF） - Analog Devices

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EVAL-ADT75EBZ
(Rev.:RevB)

±1°C Accurate, 12-Bit Digital Temperature Sensor

Analog Devices 

ADT75

Data Sheet

TIMING SPECIFICATIONS AND DIAGRAM

Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters

improves the transfer rate but has a negative effect on the EMC behavior of the part.

TA = TMIN to TMAX, VDD = 2.7 V to 5.5 V, unless otherwise noted.

Table 3.

Parameter1

Min Typ

Serial Clock Period, t1

2.5

Data In Setup Time to SCL High, t2

50

Data Out Stable After SCL Low, t3

0

Data Out Stable After SCL Low, t3

0

SDA Low Setup Time to SCL Low (Start Condition), t4

50

SDA High Hold Time After SCL High (Stop Condition), t5 50

SDA and SCL Rise Time, t6

SDA and SCL Rise Time, t6

SDA and SCL Fall Time, t7

Capacitive Load for each Bus Line, CB

1 Guaranteed by design and characterization; not production tested.

2 This time has to be met only if the master does not stretch the low period of the SCL signal.

Max

0.92

3.452

300

1000

300

400

Unit

µs

ns

ns

µs

ns

ns

ns

ns

ns

pF

Test Conditions/Comments

Fast mode I2C. See Figure 2

See Figure 2

Fast mode I2C. See Figure 2

Standard mode I2C. See Figure 2

See Figure 2

See Figure 2

Fast mode I2C. See Figure 2

Standard mode I2C. See Figure 2

See Figure 2

SCL

SDA

DATA IN

SDA

DATA OUT

t1

t4

t2

t5

t3

t7

t6

Figure 2. SMBus/I2C Timing Diagram

Rev. B | Page 6 of 24

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