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ADUM3190 查看數據表(PDF) - Analog Devices

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ADUM3190 Datasheet PDF : 16 Pages
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Data Sheet
high. The output of the ADuM3190 drives the COMP pin of
the PWM controller, which is designed to reset the PWM latch
output to low only when its COMP pin is low. A high at the
COMP pin has the effect of making the latching PWM com-
parator produce a PWM duty cycle output. This PWM duty
cycle output drives the power stage to increase the VOUT voltage
until it returns to regulation.
PWM CONTROLLER
OSC
VREF
ERROR
AMP
LATCHING
PWM
FB COMP
CURRENT
SENSE
VIN
POWER
STAGE
LO DCR
VOUT
CO +
ESR
EAOUT2
COMP
C1
COMPENSATION
NETWORK
C2 R2
OP AMP –IN
+IN
ADuM3190 1.225V REFOUT
Figure 23. Application Block Diagram 1
The power stage output is filtered by output capacitance and, in
some applications, by an inductor. Various elements contribute
to the gain and phase of the control loop and the resulting stability.
The Output Filter L and Output Filter C components create a
double pole; the op amp has a pole at 10 MHz (see Figure 21),
and the linear isolator has a pole at 400 kHz (see Figure 21 and
Figure 22).
The output capacitor and its ESR can add a zero at a frequency
that is dependent on the component type and values. With the
ADuM3190 providing the error amplifier, a compensation
network is provided from the −IN pin to the COMP pin to
compensate the control loop for stability. The compensation
network values depend on both the application and the com-
ponents that are selected; information about the component
network values is provided in the data sheet of the selected
PWM controller.
The ADuM3190 has two different error amplifier outputs,
EAOUT and EAOUT2. The EAOUT output, which can drive ±3 mA,
has a guaranteed maximum high output voltage of at least 2.4 V,
which may not be enough to drive the COMP pin of some PWM
controllers. The EAOUT2 pin can drive ±1 mA and has an output
range that guarantees 5.0 V for a VDD1 voltage range of 10 V to
20 V, which works well with the COMP pin of many PWM
controllers.
In an application where the 5 V minimum output of the EAOUT2
pin is not enough to drive the COMP pin of some PWM con-
trollers, for example, controllers that operate with 6 V or more
of COMP pin voltage, use EAOUT2 to drive the FB pin of the error
amplifier of the PWM controller (see Figure 24). The typical VREF
voltage level of PWM controllers is approximately 1.25 V or
2.5 V, setting the reference level for the FB pin. In Figure 24, the
ADuM3190
EAOUT2 output is used for a PWM controller with a 2.5 V
reference.
PWM CONTROLLER
OSC
VREF
ERROR
AMP
LATCHING
PWM
FB COMP
CURRENT
SENSE
VIN
POWER
STAGE
EAOUT2
C1 COMPENSATION
C2 R2
NETWORK
COMP
OP AMP
LO
–IN
+IN
DCR VOUT
CO +
ESR
ADuM3190 1.225V REFOUT
Figure 24. Application Block Diagram 2
As shown in Figure 24, the ADuM3190 op amp has the feed-
back voltage from the VOUT output divider is connected to the
+IN pin, and the +1.225 V reference voltage connected to the
−IN pin. This configuration produces a low going ADuM3190
COMP pin when the VOUT voltage drops from a load step. The
EAOUT2 pin follows the COMP pin, going low and connecting to
the PWM controller FB pin. The error amplifier of the PWM
controller has a reference (VREF) at the noninverting input,
which, when the FB pin is low, makes the COMP pin of the
error amplifier output go high. A high at the COMP pin causes
the latching PWM comparator to produce a PWM duty cycle
output. This PWM duty cycle output drives the power stage to
increase the VOUT voltage until it returns to regulation.
The application block diagrams (see Figure 23 and Figure 24)
show two different ways to use the ADuM3190 to provide iso-
lated feedback in the control loop of an isolated dc-to-dc converter.
In both figures, the loop is closed at approximately the 1.225 V
reference voltage, providing ±1% accuracy over temperature. The
ADuM3190 op amp has a high gain bandwidth of 10 MHz to
allow the dc-to-dc converter to operate at high switching speeds,
enabling smaller values for the Output Filter L and Output Filter C
components.
The 400 kHz bandwidth of the ADuM3190 error amplifier output
offers faster loop response for better transient response than the
typical shunt regulator and optocoupler solutions, which typically
have bandwidths of only 25 kHz to 50 kHz maximum.
SETTING THE OUTPUT VOLTAGE
The output voltage in the application circuit can be set with two
resistors in a voltage divider, as shown in Figure 25.
The output voltage is determined by the following equation,
where VREF = 1.225 V:
VOUT = VREF × (R1 + R2)/R2
(1)
Rev. 0 | Page 13 of 16

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