ADV7174KCP 查看數據表（PDF） - Analog Devices

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ADV7174KCP

Chip Scale PAL/NTSC Video Encoder with Advanced Power Management

Analog Devices 

Mode 2: Master Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7174/ADV7179 can generate horizontal

and vertical SYNC signals. A coincident low transition of both

HSYNC and VSYNC inputs indicates the start of an odd field. A

VSYNC low transition when HSYNC is high indicates the start

of an even field. The BLANK signal is optional. When the

ADV7174/ADV7179

BLANK input is disabled, the ADV7174/ADV7179 automatically

blanks all normally blank lines as per CCIR-624. Mode 2 is

illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29

illustrates the HSYNC, BLANK, and VSYNC for an even-to-

odd field transition relative to the pixel data. Figure 30

illustrates the HSYNC, BLANK, and VSYNC for an odd-to-

even field transition relative to the pixel data.

HSYNC

VSYNC

BLANK

PIXEL

DATA

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Cb Y Cr Y

Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC

BLANK

PIXEL

DATA

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

Cb

Y

Cr

Y

Cb

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

Rev. B | Page 23 of 52

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