ADXL346 查看數據表（PDF） - Analog Devices
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ADXL346 Datasheet PDF : 40 Pages
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I2C
With CS tied high to VDD I/O, the ADXL346 is in I2C mode,
requiring a simple 2-wire connection as shown in Figure 39.
The ADXL346 conforms to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 11 and
Table 12 are met. Single- or multiple-byte reads/writes are sup-
ported, as shown in Figure 40. With the ALT ADDRESS pin (Pin 7)
high, the 7-bit I2C address for the device is 0x1D, followed by the
R/W bit. This translates to 0x3A for a write and 0x3B for a read.
An alternate I2C address of 0x53 (followed by the R/W bit) can
be chosen by grounding the ALT ADDRESS pin. This translates
to 0xA6 for a write and 0xA7 for a read.
There are no internal pull-up or pull-down resistors for any
unused pins; therefore, there is no known state or default state
for the CS or ALT ADDRESS pin if left floating or unconnected.
It is required that the CS pin be connected to VDD I/O and that
the ALT ADDRESS pin be connected to either VDD I/O or GND
when using I2C.
ADXL346
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I2C is 800 Hz and scales linearly with
a change in the I2C communication speed. For example, using I2C
at 100 kHz would limit the maximum ODR to 200 Hz. Operation
at an output data rate above the recommended maximum may
result in an undesirable effect on the acceleration data, including
missing samples or additional noise.
VDD I/O
ADXL346
RP
CS
SDA
ALT ADDRESS
SCL
RP PROCESSOR
D IN/OUT
D OUT
Figure 39. I2C Connection Diagram (Address 0x53)
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary for
proper I2C operation. Refer to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, when selecting pull-up
resistor values to ensure proper operation.
Table 11. I2C Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
Low Level Output Current (IOL)
Pin Capacitance
Test Conditions
VIN = VDD I/O
VIN = 0 V
VDD I/O < 2 V, IOL = 3 mA
VDD I/O ≥ 2 V, IOL = 3 mA
VOL = VOL, max
fIN = 1 MHz, VIN = 2.6 V
1 Limits are based on characterization results; not production tested.
Min
0.7 × VDD I/O
−0.1
3
Limit1
Max
0.3 × VDD I/O
0.1
0.2 × VDD I/O
400
8
Unit
V
V
μA
μA
V
mV
mA
pF
SINGLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
STOP
ACK
MULTIPLE-BYTE WRITE
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
ACK
DATA
ACK
DATA
SINGLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
MULTIPLE-BYTE READ
MASTER START SLAVE ADDRESS + WRITE
SLAVE
ACK
REGISTER ADDRESS
START1
ACK
SLAVE ADDRESS + READ
ACK
1THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
NOTES
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 40. I2C Device Addressing
Rev. 0 | Page 17 of 40
STOP
ACK
DATA
NACK STOP
DATA
ACK
DATA
NACK STOP
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