ADXL375 查看數據表（PDF） - Analog Devices
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ADXL375 Datasheet PDF : 32 Pages
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Data Sheet
ADXL375
Table 14. I2C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Limit1, 2
Parameter Min
Max
Unit
Description
fSCL
400
kHz
SCL clock frequency
t1
2.5
µs
SCL cycle time
t2
0.6
µs
SCL high time
t3
1.3
µs
SCL low time
t4
0.6
µs
Hold time for start/repeated start condition
t5
t63, 4, 5
100
ns
0
0.9
µs
Data setup time
Data hold time
t7
0.6
µs
Setup time for repeated start condition
t8
0.6
µs
Setup time for stop condition
t9
1.3
µs
Bus-free time between a stop condition and a start condition
t10
300
ns
Rise time of SCL and SDA when receiving
0
ns
Rise time of SCL and SDA when receiving or transmitting
t11
300
ns
Fall time of SCL and SDA when receiving
250
ns
Fall time of SCL and SDA when transmitting
Cb
400
pF
Capacitive load for each bus line
1 Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
2 The timing values are referred to the input thresholds (VIL and VIH) given in Table 13.
3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data during the transmission and acknowledge phases.
4 To bridge the undefined region of the falling edge of SCL, a transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with
respect to VIH, MIN of the SCL signal).
5 The maximum value for t6 must be met only if the device does not stretch the low period (t3) of the SCL signal. The maximum value for t6 is a function of the clock low
time (t3), the clock rise time (t10), and the minimum data setup time (t5(MIN)). This value is calculated as t6(MAX) = t3 − t10 − t5(MIN).
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t7
t1
REPEATED
START
CONDITION
Figure 30. I2C Timing Diagram
t8
STOP
CONDITION
Rev. 0 | Page 19 of 32
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