ALC202 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

ALC202

AC97 Audio CODEC

Unspecified 

Avance Logic, Inc.

ALC202

Parameter

Symbol Min

Typ

BIT_CLK rise time

Triseclk

-

-

BIT_CLK fall time

Tfallclk

-

-

SYNC rise time

Trisesync

-

-

SYNC fall time

Tfallsync

-

-

SDATA_IN rise time

Trisedin

-

-

SDATA_IN fall time

Tfalldin

-

-

SDATA_OUT rise time

Trisedout

-

-

SDATA_OUT fall time

Tfalldout

-

-

Note 1: 75pF external load (50 pF in AC’97 rev2.1)

Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)

Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)

Max

Units

6

ns

6

ns

6

ns

6

ns

6

ns

6

ns

6

ns

6

ns

6.2.6 AC-Link Low Power Mode Timing:

Fig 6.2.6-1 AC-Link low power mode timing diagram

Parameter

End of slot 2 to BIT_CLK,

SDATA_IN low

Symbol Min

Typ

Ts2_pdown

-

-

Max

Units

1.0

us

6.2.7 ATE Test Mode:

Fig 6.2.6-1 ATE test mode timing diagram

*To meet AC’97 rev2.2, there are EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in

test mode.

Parameter

Symbol Min

Typ

Max

Units

Setup to trailing edge of

Tsetup2rst 15.0

-

RESET# (also applies to SYNC)

-

ns

Rising edge of RESET# to Hi-Z Toff

-

delay

-

25.0

ns

- 25 -

Rev0.62

http://www.realtek.com.tw

Preliminary

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