UPD43256BGW 查看數據表（PDF） - NEC => Renesas Technology

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UPD43256BGW

256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT

NEC => Renesas Technology 

Write Cycle Timing Chart 1 (WE Controlled)

µPD43256B

Address (Input)

CS (Input)

WE (Input)

I/O (Input/Output)

tWC

tCW

tAW

tAS

tWP

tWR

tWHZ

Indefinite data out

High

impe-

dance

tOW

tDW

tDH

Data in

High

Indefinite data out

impe-

dance

Cautions 1. CS or WE should be fixed to high level during address transition.

2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite

in phase with output signals.

Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.

2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,

read operation is executed. Therefore OE should be at high level to make the I/O pins high

impedance.

3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins

will remain high impedance state.

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