HYB39S256160T-8B 查看數據表（PDF） - Infineon Technologies
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HYB39S256160T-8B Datasheet PDF : 46 Pages
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HYB39S256400/800/160T
256MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Device CKE CKE DQM BS0 AP= Addr CS RAS CAS WE
State n-1 n
BS1 A10 .
Idle3
H
X
X
V
V
V
L
L
H
H
Bank Precharge
Any
H
X
X
V
L
X
L
L
H
L
Precharge All
Any
H
X
X
X
H
X
L
L
H
L
Write
Active3 H
X
X
V
L
V
L
H
L
L
Write with Autoprecharge Active3 H
X
X
V
H
V
L
H
L
L
Read
Active3 H
X
X
V
L
V
L
H
L
H
Read with Autoprecharge Active3 H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle
H
X
X
V
V
V
L
L
L
L
No Operation
Burst Stop
Any
H
X
X
X
X
X
L
H
H
H
Active4 H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
Auto Refresh
Idle
H
H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
H
X
X
X
(Self
Refr.)
L
H
X
X
X
X
L
H
H
X
Clock Suspend Entry
Active H
L
X
X
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Idle
H
X
X
X
Active5 H
L
X
X
X
X
L
H
H
X
Clock Suspend Exit
Active L
H
X
X
X
X
X
X
X
X
Power Down Exit
Any
H
X
X
X
(Power L
Down)
H
X
X
X
X
L
H
H
L
Data Write/Output Enable Active H
X
L
X
X
X
X
X
X
X
Data Write/Output Disable Active H
X
H
X
X
X
X
X
X
X
Note:
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before
the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Device state is Full Page Burst operation, which is not supported on this device.
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle
device is clock suspend mode.
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