AM29LV160BB-120 查看數據表（PDF） - Advanced Micro Devices

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AM29LV160BB-120

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29LV160B Device Bus Operations

Read

Write

Operation

Standby

Output Disable

Reset

Sector Protect (Note 2)

CE# OE# WE# RESET#

L

LH

H

L

HL

H

VCC ±

0.3 V

X

X

VCC ±

0.3 V

L HH

H

X XX

L

L

HL

VID

Sector Unprotect (Note 2)

L

HL

VID

Temporary Sector

Unprotect

X XX

VID

Addresses

(Note 1)

AIN

AIN

X

X

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Address,

A6 = H, A1 = H,

A0 = L

AIN

DQ0–

DQ7

DOUT

DIN

DQ8–DQ15

BYTE#

= VIH

DOUT

DIN

BYTE#

= VIL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z High-Z

High-Z

High-Z High-Z

High-Z High-Z

High-Z

High-Z

DIN

X

X

DIN

X

DIN

DIN

X

High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at VIH. The BYTE# pin determines whether the

device outputs array data in words or bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware re-

set. This ensures that no spurious alteration of the

memory content occurs during the power transition.

No command is necessary in this mode to obtain

array data. Standard microprocessor read cycles that

assert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. ICC1 in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

10

Am29LV160B

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