GTL2002 查看數據表（PDF） - Philips Electronics
零件编号
产品描述 (功能)
生产厂家
GTL2002 Datasheet PDF : 24 Pages
| |||
FREQUENTLY ASKED QUESTIONS
Device
1. Question: The GTL-TVC schematic makes these parts look like an array of NMOS transistors?
Answer: Yes, the GTL 2000, 2010 and 2002 are arrays of NMOS transistors with a common gate. These parts could
be used as one large NMOS transistor by wiring all the sources together and all the drains together. However, they
were designed as level shifters /clamps where the inherent matching is used by making one transistor a reference and
the remaining transistors as level shifters/clamps. Not shown in the schematic are the ESD protection devices
between each pin and ground.
2. Question: Can any transistor in the array be used as the reference transistor?
Answer: Yes, any transistor can be used as long as its Dn pin is connected to the GREF pin and its associated Sn is
used as the SREF. However, the DREF pin is probably the easiest to use because of its close proximity to the GREF
pin.
3. Question: Are the Sn and Dn pins interchangeable?
Answer: Yes, the Sn and Dn labels are merely for convenience in thinking about the devices. A Sn pin could be
used as a drain and the corresponding Dn pin used as a source. The n indicates a number, which identifies a
transistor. Thus, S1 and D1 correspond to transistor 1.
4. Question: Are both the Sn and Dn ports 5-V I/O tolerant?
Answer: Yes, both the ports are 5.5 V tolerant, and the GREF is also 5.5 V tolerant.
5. Question: Do the GTL-TVC devices isolate the capacitance in the line?
Answer: No, the devices don't have this capability since the device is basically an array of NMOS transistors.
6. Question: What will be the typical propagation delay for GTL2000 device family?
Answer: The GTL2000 family of devices have the propagation delay associated with a 5 Ω wire for much of the
swing. Thus with a 50 pF load and a low resistance driver driving the transition and measuring both sides at the
same voltage level i.e. 1.5 V, the delay is about 0.25 ns. If the delay wanted is from one side GTL+ where the
measurement point is 1 V to CMOS at 5 V in the other side, with a 2.5 V measurement voltage, then the delay is not
the 0.25 ns of the GTL2000 family part. It is rather primarily the delay of the system, that is the RC time constant of
the pull-up and the line capacitance, which determine the rise time between 1 V and 2.5 V. The fall time is not
affected as much because the driver's effective resistance is very low compared to the pull-up so the 2.5 V to 1 V
transition is much faster than the rising transition. For a 3 V to 5 V level translation, the measurement point
difference is much less so the propagation delay is shorter. If the 5 V part is TTL input then the measurement points
are the same.
7. Question: I am using a 3.3 V FPGA with a GTL device on some pins. The GTL device does the level conversion,
either down to 1.8V or up to 5V. The pins from the GTL device go to a connector. There is a possibility that a
human being touches it and there a ESD can occur. Will GTL prevent the FPGA from ESD? I think that the GTL
device is ESD protected, am I right?
Answer: The GTL2000/10/02 devices all have ESD protection > 2kV HBM and they should absorb most of the
energy from an ESD event. The GTL part on the connector will absorb the primary ESD energy but we cannot
guarantee that this will always protect the FPGA. Very little of the ESD energy should reach the FPGA however.
8. Question: Due to the requirement of the voltage for the 200 kΩ pull-up at both the GREF and DREF pins that has to
be at least 1.5V more than the SREF voltage (1.8V in this case), the voltage at the 200 kΩ resistor need to be at least
3.3V. The design does not have such voltage provided other than 1.8V and 3.0V. Can the GTL2010 be used?
Answer: The device will work with 1.2V differential but the actual voltage seen on the lower side may not be what
SREF sets. Example would be one side at 5V and the other at 3V; you will always seen 5V and 3V. If one side is at
5V and the other at3.8V, then you will always seen 5V but may see > 3.8V on the other side depending on current
flow. The higher voltage may not matter much unless the device in not tolerant to the higher voltage. You could also
adjust the SREF to the low side of the band so that the overshoot doesn't over stress the device. The problem is not
that the 3.8 V side would be above 3.8 V but rather that it might only get as high as 3.5 V and that the exact value
will vary from part to part and would be between 3.5 V and 3.8 V. Or in the specific case the 1.8 V side high may
15
Share Link: 