GTL2010PW-T 查看數據表（PDF） - Philips Electronics
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GTL2010PW-T Datasheet PDF : 24 Pages
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S1 switching from High to Low and input S2 switching from Low to High, output D1’s waveform is markedly
different from D1’s output when S1 and S2 both switch from High to Low. The waveform looks a lot better with
SREF (1.3 V) greater than the CPU I/O voltage (1.1 V), but because of process reliability issues the Serf” voltage
cannot be greater than the CPU supply voltage.
Answer: The GTL2000 is specified at 15.2 mA with the SREF at 1.365 V with the Dn at 0.175 V. When the SREF
is at 1.1 V, the on resistance of the channel is degraded. The observation being referred to is that if both channels
make a high to low transition at the same time the fall time of the Dn side is slower than if one is falling and the
other is rising.
There are 2 reasons for this observation:
1. First is that there is some capacitive coupling between the drain and the gate and between the source and the
gate. When the channels have opposite transitions, the coupled charges cancel out. When they are in the same
direction they perturb the voltage on the GREF node making the channels weaker to pull the Dn nodes down.
Role of the capacitor on the GREF node is to minimize this effect, however because the GREF pin has package
inductance and the ESD protection includes some series resistance, the decoupling capacitor benefit is limited.
2. Second is that a SREF at 1.1 V results in an effective lower gate overdrive voltage, so the on resistance is
higher. The 300 kΩ resistor to the 3.3 V supply biases the GREF to just a threshold above the SREF voltage. In
the case of SREF = 1.1 V rather than SREF = 1.365 V the GREF will be 0.265 V lower.
Possible techniques to improve the behavior:
1. Include larger decoupling capacitor. This slows down the RC time constant of the GREF node.
2. Lower the value of the bias resistor so that it provides more charging current for the GREF node. It will also
increase the leakage current at Sn = SREF.
3. Decrease the Sn low voltage to compensate for the higher on resistance.
4. Operate the channel at a lower current by raising the high voltage side resistor. This trades High to Low for
Low to High delay.
5. Double up on channels (combine two I/Os), this increases the capacitance at the level shifter because of the two
channels and reduces the on resistance.
7. Question: Why did we use GREF at 3.3V and inputs on that side at 2.5V for the timing test setup and why not 2.5V
on GREF and the inputs to 1.5V SREF or 3.3V GREF and inputs to 1.5V SREF?
Answer: The Vref or SREF for the test circuit is 1.365 V to 1.635 V, with the GREF and DREF connected together
and tied through a 200 kΩ resistor to 3.3 V so the difference is 1.66 V which satisfies the 1.5 V requirement and the
translation is 1.5 V (1.365 - 1.635) to 2.5 V. For the 2.5 to 3.3 V case, the resistor to GREF should be to 4 V or
higher if 3.3 V is used the low side high voltage will be degraded below the 2.5 V on the SREF.
Applications
1. Question: Can I use the GTL2010 to level shift from 1.5 V to 3.3 V and from 1.5 V to 5 V at the same time?
Answer: Yes, as long as the low side high voltage is the same for both translations, in this case 1.5 V. In this case,
the SREF can be connected to 1.5 V and different transistors used, i.e. source side on the 1.5 V level and the drain of
one at 3.3 V and the drain of the other at 5.0 V as shown in Figure 16. The Pull up resistors would need to be sized
so as not to exceed the maximum allowed current (i.e., 15 mA) for the GTL-TVC device.
2. Question: How does the GTL-TVC device act like a termination for the GTL line?
Answer: GTL and GTL+ logic families rely on incident wave switching which require the line to be terminated at
the end with a resistor equal to the effective Z0 of the line to prevent reflections. The line in GTL /GTL+ systems is
generally used point to point with one termination resistor but could be use on a bus with multiple drivers, so it is
driven from the middle and termination is required at both ends. The GTL-TVC device can be used in place of the
termination at an end by sizing the resistor on the high voltage side (Dn side) to provide the same low state current
that the termination resistor would have provided (i.e., GTL/GTL+ is about 15 mA).
3. Question: I have worked with the Intel 845 Northbridge chipset and I’m trying to use the GTL-TVC translators to
interface a standard 3.3V PCI chip to the 1.5 V AGP bus of the i845. Any information related to my application
would be appreciated.
Answer: The Intel reference design doesn't use the same resistor values as we recommend. They use 1 kΩ for the
1.5 V side and 2.2 kΩ for the 3.3 V and 5 V side. GREF and DREF are connected together with a 200 kΩ resistor.
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