GTL2002D 查看數據表（PDF） - Philips Electronics

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GTL2002D

Bi-directional low voltage translators

Philips Electronics 

Use SREF to clamp the Sn port at 1.5 V so the 3.3 V Dn port side signal is clamped at 1.5V without having to use

any pull up resistors on the lower voltage side. When going from 1.5 V to 3.3 V a pull up resistor has to be used on

the 3.3 V Dn port side. The GTL-TVC devices don't have a direction pin that makes them very nice for bi-

directional level translation.

The timing budget in AGP is quite tight so devices have to be as fast as possible. Both AGP and PCI do not have a

signal to control the direction of the data so devices that don't have a direction pin (e.g., GTL-TVC) are very

convenient.

Regarding the pull-up on the PCI side, in a typical PCI environment, only the control signals need pull-ups and those

are provided by the motherboard. The stability of the rest of the signals is guaranteed by parking the bus. In the case

where the PCI chip is not connected to the motherboard PCI bus, pull-up resistors on the control signals are

required.

4. Question: Both the PCI 3.3 V and AGP 1.5 V are push-pull logic and most of the signals are bi-directional. For me

it's clear that going from AGP 1.5 V to PCI 3.3 V needs pull up resistors to pull the signals up, so I need pull-ups on

the PCI side. From the PCI 3.3 V side to the AGP 1.5 V we only need to clamp signals so my question is: Can I save

the pull-ups on the AGP side?

Answer: Yes, a pull-up is not required on the AGP 1.5 V side unless there are reflection related noise problems. If

this is a GTL application with incident wave switching where typically both ends of the bus are terminated with the

characteristic impedance of the bus, the GTL-TVC translator will replace one of the terminations. Unless the AGP

edge rates are fast enough or the data rate is so high that the line needs to be terminated at both ends, the GTL20XX

translators can provide the pull-up using current from the 3.3 V side and no pull up resistors are needed on the 1.5 V

side.

5. Multi-part Question :

We want to use the Philips GTL2010 for level shifting between Intel GMCH DVO @ 1.5 V and our TV Encoder @

3.3 V. The diagram shown in Figure 17 is the reference circuit recommended by the TV encoder vendor. In the

recommended circuit, there are two levels of voltage shifting, 1.5 V to 3.3 V and 1.5 V to 5 V. We will only use the

level shifting of 1.5 V to 3.3 V by putting GREF (pin 24) and DREF (pin 23) to 3.3 VDD. The signal running through

the GTL2010 is the Open Drain I2C Bus, bi-directional for the I2C data and uni-directional for the I2C clock.

Question A: Do you think that the circuit shown in Figure 17 is well designed? Do you have an advice for the

design?

Answer A: You could try removing the pull up resistors on the 1.5 V side since the 3.3 V pull ups pass through the

device and will pull the 1.5 V line high to the clamping voltage of 1.5 V. You can also leave them on since it will

not hurt.

Question B: VSn (ON-state) = 0.2 V max, VDn (ON-state) = 0.4 V max. Is this the input specification?

Answer B: VSn is describing an input condition, VDn is describing the corresponding output condition. That is if a

low of 0.2 V is forced on the Sn pin the corresponding Dn will be 0.4 V or less (but not less than Sn) for the pull-up

currents within the data sheet.

Question C: If 0.5 V is applied to the Sn, doesn’t the FET become ON-state because VSn (ON-state) is 0.2 V

maximum?

Answer C: The data path is a large NMOS transistor, where the gate is nominally biased to a threshold above the

reference source. Anytime that an Sn pin is forced to a voltage below the SREF the NMOS transistor will be on. The

lower the Sn voltage the lower the on resistance. That is if the SREF is at 1.5 V and the GREF and DREF are

connected together and a current limiting resistor of 200 kΩ connects between a 3.3 V supply and the GREF/DREF

node. Then, if an Sn pin is pulled below 1.5 V the corresponding Dn will start to pull current. The closer to 0.0 V

that the Sn gets the more current the Dn will pull, or, described as on-resistance, the lower the Sn voltage the lower

the on-resistance.

Note: the lower the SREF voltage the higher the effective on-resistance, because the effective VGS - Vt is less since

the VG follows the SREF voltage.

Question D: The On-state values are not dependant on Vs-ref but on the current through the device. I do not

understand why on-state value is not dependant on Vs-ref. Could you tell me the reason in detail? I think that if Vs-

ref is up, then Vg of the FET is up and then voltage difference between Vg and Vsn will become large, therefore the

Vsn maximum voltage is more than 0.2 V.

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