GTL2002 查看數據表（PDF） - Philips Electronics

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GTL2002

Bi-directional low voltage translators

Philips Electronics 

Answer D: The voltage drop between Sn and Dn depends upon both current and the difference between Vs-ref and

the voltage at Sn. For a specific selection of Vs-ref and Vsn, the voltage at Dn depends on the current. If the voltage

of the SREF pin is raised, the necessary voltage on the Sn pin will rise if the same current and voltage drop between

Sn and Dn are considered. If the voltage at Dn is considered fixed and the same current is needed, the Sn can only

move up slightly even if the SREF is raised substantially.

Question E: When voltage of Sn is more than Vs-ref (V), the FET is high impedance and when voltage of Sn is less

than 0.2V, the FET is low impedance. Is this correct? By the way, I would like to know the relationship between

FET impedance versus voltage of Sn (or Dn) or FET impedance versus current through the FET. Do you have any

measurement data?

Answer E: Yes, see Figures 8 to 13. When Sn = SREF, the bias circuit sets the current to a few microamperes, thus

off, and for any Sn voltage above SREF, the leakage decreases.

Question F: Please see the DC specification of our product circuit. Could you tell me your opinion whether this

circuit works correctly? If not, could you advise?

Answer F: The TV Encoder's Vol of 0.4 V @ 2.0 mA limits the resistor choices because the current on the TV

Encoder side must not exceed 2.0 mA. If the 2.0 mA is divided into equal contributions from both the 1.5 V and 3.3

V sides, a minimum value of 1.1 kΩ on the 1.5 V side and a minimum value of 3 kΩ on the 3.3 V side are needed.

Higher value resistors could be used at the expense of increasing the RC time constants. If the power supply ranges

were ± 10 % (i.e., 3.3 V ± 0.3 V) then the minimum resistor value would be set by the high supply limits (3.3 kΩ on

the 3.6 V (max) and 1.2 kΩ on the 1.65 V (max) side).

6. Question: On the GTL2002 parts, if you have a uni-directional signal that is being driven by an OR gate, can this

net be put directly into the part on the TTL side, or do you have to have the inputs all open drain with pull-up

resistors? I would expect this be all right since there is no way the microprocessor will drive this signal low and

short a ground to a driven signal.

Answer: The only possible problem is if the OR gate output drive is very strong (i.e. fast edge rates), it may be

desirable to add a series termination resistor to the output of the OR gate to prevent ringing and an over voltage at

the microprocessor caused by ringing. If the OR gate does not have fast edge rates there should be no problems. The

GTL2002 will prevent any static over voltage of the microprocessor input but if the edge rate is too fast there may

be some dynamic over voltage. Configuration is as following: SREF connected to the microprocessor power supply,

DREF connected to GREF and to a high value resistor (200 kΩ) to a power supply at least 1.5 V above the

microprocessor supply, and uni-directional down translation).

7. Question: We need a translator to convert signals from 5V to 3.3V and vice-versa. But the drivers are not open-

drain. In this case, can I use GTL2000?

Answer: If the drivers are not open drain, you system needs to integrate some flag between the driving devices so

there is no conflict by having one device driving a high level while at the same time the other one is driving a low

level. There needs to be a way to prevent bus contention otherwise the devices would be damaged. With that in

mind, the GTL2000 can be used.

8. Question: Is the GTL2000/02/10 capable of supporting I2C voltage level shifting in the Standard-speed mode

(100kbits/s), Fast-speed mode (400kbit/s) and/or High-speed mode (3.4Mbits/s)?

Answer: The GTL bi-directional voltage level translators are essentially frequency independent. So they should

work at all three speeds. However, in addition to some series resistance, it also adds some capacitance to the wire.

This is not a problem for the Standard mode or Fast mode, although it needs to be added to the total line capacitance.

For the High-speed mode, the extra capacitance is probably undesirable, but the translators will communicate the

signal if the rest of the capacitance is small enough.

Note: During a low to high event in the High-speed mode, the master's current source pull up will not up translate

through the GTL voltage level translators. That is if the master is on the low voltage side of the translator, the

current source pull-up (active pull-up) will only pull-up the low voltage side of the bus because on the high voltage

side of the translator, the high speed current source pull-up will cut off just below the clamp voltage (SREF), leaving

only the normal pull up resistor on the high voltage side to complete the low to high transition (SREF to Vcc).

9. Question: GTL20xx in AGP applications. So far, the AGP specification is version 2.0 and the signal is specified at

1.5V. In AGP specification 3.0, the signal will migrate to a 0.8V swing and I think this will be a problem using the

GTL20xx devices. Why was the low limit of the GTL20xx set at 1V? Could it be used at 0.8V?

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