GTL2010BS-T 查看數據表（PDF） - Philips Electronics
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GTL2010BS-T Datasheet PDF : 24 Pages
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SREF at 3.3 V. The effect is that the maximum high level that will be passed by the clamp is slightly above 3.3
V, whether the 5 V signals are applied to Sn or Dn pins.
Question B: Due to battery operation, we cannot afford to have 16mA pull-up current on 48 signals as this would
result to current >700mA under certain conditions, so we opt for 3 to 4 mA per signal as a maximum.
- How would that influence the speed?
- What speed can I expect (in terms of rising/falling edges and frequency) and is the speed dependant on the
value of pull-up resistors (higher resistors than recommended are used)?
- Is the speed influenced by RPULL-UP x CTOTAL or is the matter more complex?
- I use a FPGA that is 3.3V device with 5 V tolerant I/O’s. It has internal (active) pull-ups. Can I rely on them
(use them) when translating from 1.8V to 3.3V (up conversion) or from 5V to 3.3V (down conversion)?
Answer B: The speed, that is the rise time is directly the RC product, so higher resistors will result in a slower
behavior. For bi-directional signal operation it is necessary to use passive pull-ups or have an external circuit
prevent contention between a low on one side with a high on the other side. If signals are flowing in only one
direction on some lines the active pull-up on those lines cannot result in a contention because only one side has a
driver. If the signal is being driven from the higher voltage logic to the lower voltage logic input the active pull-up is
all that is needed, however if the low voltage logic is the driver, it will be necessary to use a pull-up on the high
voltage logic side in order for the high level to reach a full high. An open drain bus is the easiest way to handle
bidirectional signals, however it requires passive pull-ups. A more exotic alternative to resistors is use of current
sources because they give a faster rise for the same worst-case maximum current.
12. Question: Is it possible to have the GTL2000 with 2.5V and 3.3V on one side and 5V on the other side?
Answer: Yes, if the 2.5 V and 3.3V low side voltages are present at different times / applications, the SREF could
be used to connect to the current low side voltage. If both 2.5 V and 3.3 V voltages are present at the same time on
the low voltage side with 5.0 V on the high voltage side, the SREF will need to be connected to the lowest voltage,
2.5 V in this case, and the voltage that will be passed on the 3.3 V pins would be 2.5 V. Pull up resistors could be
used on the 3.3 V pins to achieve 3.3 V. The unidirectional or bidirectional voltage can be applied on a per channel
basis. The idea of bi-directional is that there are drivers on both sides of the GTL2000 that can be active, so the
signal can flow in either direction. If the outputs are totem pole outputs, some mechanism is required to prevent the
contention of a high level on one side with a low level on the other. The use of open drain outputs eliminates the
possibility of such a contention. Uni-directional means only one side of each channel has a driver so contention is
not possible. Different channels in the same GTL2000 can be operated as bi-directional, uni-directional up
translation or uni-directional down translation, and the high side voltages can differ, but the SREF must be
connected to the low side voltage in order to clamp to that voltage.
13. Multi-part Question:
Question A: I have been looking at using the GTL2000 for a 2.5-V FPGA to 5-V Sensor drive.
Here's my configuration: the FPGA has to drive 17 control signals to a 5 V part. The 5 V part has 2 outputs that
connect to the FPGA. The FPGA is NOT 5 V tolerant and cannot be configured to have open drain outputs. What
configuration would be best for me to use?
Answer A: The clamp voltage would be set at 2.5 V and then each Sn/Dn pair can be used in a uni-directional
(either direction) or bi-directional mode where you just need to treat each Sn/Dn pair individually. So the seventeen
2.5 V to 5 V signals would have no resistors on the 2.5 V side that are driven with the totem pole outputs and you
would need to put pull up resistors on the 5 V side so the sensor input would see 5 V H (high) when the FPGA is
driving high or L (low) when the FPGA is driving low. The 2 5 V to 2.5 V signals would not need the pull ups on
the 5 V side if the sensor has totem pole outputs and you don't need pull up resistors on the 2.5 V side if you don't
have too much leakage.
Question B: What if I was to up the FPGA output voltage and input tolerance to 3.0 V or even 3.3 V? Would the
configuration be the same except for SREF being pulled to 3.3 V instead of 2.5 V?
Answer B: Yes, this is correct.
14. Question: I want to use the GTL2010 as unidirectional conversion from 3.3 V to 1.5 V on some control signals to a
CPU. I also want to have jumper override on these signals, so I want to put on the low side an option to either pull
the signal up through a 2.2 kΩ resistor or pull down through a 2.2 kΩ resistor. If the high side is driving high and the
low side is pulled down with the 2.2 kΩ resistor, is it like having a 200 kΩ resistor pulling up with a 2.2 kΩ resistor
pulling down (200 kΩ connected between GREF, DREF to 3.3 V) thus getting a logical Low on the Low side?
I cannot connect the low side directly to GND or 1.5V.
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