AN8022L 查看數據表（PDF） - Panasonic Corporation
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AN8022L Datasheet PDF : 16 Pages
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AN8022L, AN8022SB
Voltage Regulators
s Application Notes (continued)
[2] Operation descriptions (continued)
5. Soft start (continued)
On the other hand, the VFB has high voltage because the power supply output is low. And, the VDTC is positioned
at the medium voltage of the triangular wave oscillation waveform as constant voltage. Therefore, at operation
starting, the VSS is input to the PWM comparator as the lowest voltage and is compared with the triangular wave
oscillation waveform.
As the result, the output of the IC generates the pulse of duty which gradually becomes large with the rise of
VSS from the minimum duty. (Refer to figure 7.)
However, when the VSS exceeds the VFB or VDTC , the duty of the output pulse depends on the VFB or VDTC .
The soft start function works only up to that point and after that the normal control comes.
VFB
VCT
VCT
VSS
VFB
VDTC
0V
VSS
VDTC
VFB
VOUT
0V
Figure 7. Soft start operation waveform
6. Timer latch
When the short-circuit or overload of the power supply output continues for a certain period, the pulse-by-pulse
overcurrent protection is not sufficient for protection of the transformer, Fast Recovery Diode (FRD), Schottky
Diode in the secondary side and the power MOSFET. For this reason, the timer latch function is employed, which
stops the power supply by hitting the OVP, when the overcurrent condition continues for a certain period.
The short-circuit or overload of the power supply output is monitored as the decrease of the power supply output
(at this time the pulse-by-pulse overcurrent protector is in the operating condition). The decrease of the power
supply output is detected as the decrease of current amount from the current feedback terminal of the normal
PWM control. When the decrease amount of this current exceeds a certain value, the comparator inside the IC
reverses to flow the constant current to the TIM/OVP terminal.
The external capacitor is connected to the TIM/OVP terminal. Electric charges are accumulated in this capacitor
to rise the OVP terminal voltage. When the OVP operating threshold voltage (6 V typical) is reached, the OVP starts
operation to stop the IC and keeps this stop condition. (Refer to Figure 8.)
• Timer period
The period from the time when an error of the power supply output is detected to the time when the OVP starts
operation (hereinafter referred to as timer period) should be longer than the rise time of the power supply. Since
at operation start the IC is in the same condition as the overload or output short-circuit condition, if the timer
period is shorter, the power supply works latch and can not start.
Therefore, the IC is designed so that the timer period can be set to any desired value with capacitance value of
the external capacitor connected to the TIM/OVP terminal. However, particular care should be taken, because too
large value of this capacitance may cause the breakdown of the power supply.
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