APW7067NME-TRL 查看數據表（PDF） - Anpec Electronics

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APW7067NME-TRL

Synchronous Buck PWM and Linear Controller

Anpec Electronics 

APW7067N

Application Information (Cont.)

Input Capacitor Selection (Cont.)

tested by the manufactures. If in doubt, consult the

capacitors manufacturer. For high frequency decoupling,

a ceramic capacitor 1µF can be connected between the

drain of upper MOSFET and the source of lower MOSFET.

MOSFET Selection

The selection of the N-channel power MOSFETs are

determined by the R , reverse transfer capacitance

DS(ON)

(CRSS) and maximum output current requirement. There

are two components of loss in the MOSFETs: conduction

loss and transition loss. For the upper and lower

MOSFET, the losses are approximately given by the

following:

PUPPER = IOUT1 2(1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS

PLOWER = IOUT1 2(1+ TC)(RDS(ON))(1-D)

Where IOUT1 is the load current

TC is the temperature dependency of R

DS(ON)

FS is the switching frequency

tSW is the switching interval

D is the duty cycle

Note that both MOSFETs have conduction loss while the

upper MOSFET include an additional transition loss. The

switching internal, tSW, is a function of the reverse transfer

capacitance CRSS. The (1+TC) term is to factor in the

temperature dependency of the RDS(ON) and can be extracted

from the “RDS(ON) vs Temperature” curve of the power

MOSFET.

Copyright © ANPEC Electronics Corp.

17

Rev. A.3 - Mar., 2008

www.anpec.com.tw

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