AS1310-BTDT-331 查看數據表（PDF） - austriamicrosystems AG

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AS1310-BTDT-331

Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter

austriamicrosystems AG 

AS1310

Datasheet - Application Information

Table 4. Recommended Inductors

Part Number

LQH32CN6R8M53L

LQH3NPN6R8NJ0L

LQH44PN6R8MJ0L

L

6.8µH

6.8µH

6.8µH

DCR

250mΩ

210mΩ

143mΩ

Current Rating

0.54A

0.7A

0.72A

Dimensions (L/W/T)

3.2x2.5x1.55 mm

3.0x3.0x1.1 mm

4.0x4.0x1.1 mm

Manufacturer

Murata

www.murata.com

9.5 Capacitor Selection

The convertor requires three capacitors. Ceramic X5R or X7R types will minimize ESL and ESR while maintaining capacitance at rated voltage

lid over temperature. The VIN capacitor should be 22µF. The VOUT capacitor should be between 22µF and 47µF. A larger output capacitor should

be used if lower peak to peak output voltage ripple is desired. A larger output capacitor will also improve load regulation on VOUT. See Table 5

for a list of capacitors for input and output capacitor selection.

a Table 5. Recommended Input and Output Capacitors

v Part Number

GRM21BR60J226ME99

ill GRM31CR61C226KE15

GRM31CR60J475KA01

C

22µF

22µF

47µF

TC Code

X5R

X5R

X5R

Rated Voltage

6.3V

16V

6.3V

Dimensions (L/W/T)

0805, T=1.25mm

1206, T=1.6mm

1206, T=1.6mm

t On the pin REF a 10nF capacitor with an Insulation resistance >1GΩ is recommended.

Manufacturer

Murata

www.murata.com

G s Table 6. Recommended Capacitors for REF

A t Part Number

C

GRM188R71C104KA01

s n GRM31CR61C226KE15

100nF

100nF

TC Code

X7R

X7R

Insulation

Resistance

>5GΩ

>5GΩ

Rated

Voltage

16V

50V

Dimensions (L/W/T)

0603, T=0.8mm

0805, T=1.25mm

Manufacturer

Murata

www.murata.com

m te 9.6 Layout Considerations

Relatively high peak currents of 480mA (max) circulate during normal operation of the AS1310. Long printed circuit tracks can generate

a n additional ripple and noise that mask correct operation and prove difficult to “de-bug” during production testing. Referring to Figure 1, the input

loop formed by C1, VIN and GND pins should be minimized. Similarly, the output loop formed by C2, VOUT and GND should also be minimized.

Technical co Ideally both loops should connect to GND in a “star” fashion. Finally, it is important to return CREF to the GND pin directly.

www.austriamicrosystems.com/DC-DC_Step-Up/AS1310

Revision 1.8

15 - 19

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