AS1160 查看數據表（PDF） - austriamicrosystems AG

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AS1160

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Detailed Description

Resynchronization

When the deserializer PLL locks to the embedded clock edge, the deserializer LOCKN pin asserts a low. If the deseri-

alizer loses lock, pin LOCKN output will go high and the outputs (including RCLK) will enter tri-state.

The user’s system monitors the pin LOCKN to detect a loss of synchronization. Upon detection, the system can

arrange to pulse the serializer SYNC1 or SYNC2 pin to resynchronize.

Multiple resynchronization approaches are possible. It is mandatory to provide a feedback loop using pin LOCKN to

control the SYNC request of the serializer (SYNC1 or SYNC2). Two SYNC pins are provided for multiple control in a

multi-drop application. Sending SYNCPATs for resynchronization is desirable when lock times within a specific time

are critical.

Powerdown

The low-power powerdown mode can be used while no data transfer is taking place. The serializer and deserializer

use the powerdown mode to reduce power consumption by:

- The deserializer enters powerdown when pins PWDNN and REN are low.

- The serializer enters powerdown when pin PWDNN is driven low.

In powerdown, the PLL stops and the outputs enter tri-state, which disables load current and reduces supply current to

the µA range.

Note: To exit powerdown, drive pin PWDNN high.

Before valid data exchanges between the serializer and deserializer, the devices must re-initialized and resynchro-

nized to each other. Initialization of the serializer takes a maximum of 400 TCLK cycles. The deserializer will initialize

and assert LOCKN high until lock to the Bus LVDS clock occurs.

Tri-State

The serializer enters tri-state when pin DEN is driven low. This puts both driver output pins (DO+ and DO-) into tri-

state. When DEN is driven high, the serializer returns to the previous state, as long as all other control pins remain

static (SYNC1, SYNC2, PWDNN, TCKR/FN).

When pin REN is driven low, the deserializer enters tri-state. Consequently, the receiver output pins (ROUT0:ROUT9)

and RCLK will enter tri-state. The LOCKN output remains active, reflecting the state of the PLL.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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