AS1747-BWLT 查看數據表（PDF） - austriamicrosystems AG
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产品描述 (功能)
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AS1747-BWLT
austriamicrosystems AG
AS1747-BWLT Datasheet PDF : 17 Pages
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AS1747, AS1748, AS1749, AS1750
Datasheet - Timing Diagrams
10 Timing Diagrams
Figure 19. Switching Time
VCC
VN_
lid Logic
Input
NO_
OR NC_
IN_
GND
VCC
COM_
VOUT
RL
CL
CL includes fixture and stray capacitance
VOUT = VN_(RL / (RL + RON))
va Logic VCC
Input 0V
till Switch 0V
G s Output
50%
tr < 5ns
tf < 5ns
tOFF
VOUT 0.9 x VOUT
0.9 x VOUT
IN depends on switch configuration;
Input polarity determined by sense of switch.
tON
A t Figure 20. Break-Before-Make Interval
VCC
ms ten VN_
a on Logic
c Input
NC_
NO_
IN_
VCC
COM_
VOUT
VCC
Logic
Input
0V
RL
CL
GND
CL includes fixture and stray capacitance
VOUT
50%
tBBM
0.9 x VOUT
al Figure 21. Charge Injection
ic RGEN
n +
h VGEN
NC_
OR NO_
GND
VCC
VCC
COM_
IN_
Tec VILtoVIH
ΔVOUT
VOUT
VOUT
CL
IN OFF
IN OFF
ON
ON
Q = (ΔVOUT)(CL)
OFF
OFF
Logic input waveforms inverted for switches
that have the opposite logic sense.
www.austriamicrosystems.com/Analog-Switches/AS1747-50 Revision 1.02
11 - 16
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