AS6C1008-55 查看數據表（PDF） - Alliance Semiconductor
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AS6C1008-55 Datasheet PDF : 14 Pages
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February 2007
AS6C1008
®
128K X 8 BIT LOW POWER CMOS SRAM
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25ºC
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL =30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
AS6C1008-55
MIN. MAX.
55
-
-
55
-
55
-
30
10
-
5
-
-
20
-
20
10
-
(2) WRITE CYCLE
PARAMETER
SYM.
AS6C1008-55
MIN. MAX.
Write Cycle Time
tWC
55
-
Address Valid to End of Write
tAW
50
-
Chip Enable to End of Write
tCW
50
-
Address Set-up Time
tAS
0
-
Write Pulse Width
tWP
45
-
Write Recovery Time
tWR
0
-
Data to Write Time Overlap
tDW
25
-
Data Hold from End of Write Time tDH
0
-
Output Active from End of Write
tOW*
5
-
Write to Output in High-Z
tWHZ*
-
20
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
pF
pF
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
02/February/07, v 1.0
Alliance Memory Inc.
Page 4 of 14
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