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AT24C512C

I²C-Compatiable (2-wire) Serial EEPROM 512-Kbit (65,536 x 8)

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7. Device Addressing

The 512K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a read or

write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most-significant

bits (see Figure 7-1 below). This is common to all 2-wire EEPROM devices.

The 512K uses the three device address bits, A2, A1, and A0, to allow as many as eight devices on the same bus. These

bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit

that biases them to a logic low condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a valid compare is not made, the device will

return to a standby state.

Figure 7-1. Device Address

1 0 1 0 A2 A1 A0 R/W

MSB

LSB

8. Write Operations

Byte Write: A Byte Write operation requires two 8-bit data word addresses following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then the part is to

receive an 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing

device, such as a microcontroller, then must terminate the write sequence with a Stop condition. At this time, the

EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write

cycle, and the EEPROM will not respond until the write is complete (see Figure 9-1 on page 10).

Page Write: The 512-Kbit EEPROM is capable of 128-byte page writes.

A Page Write is initiated the same way as a byte write, but the microcontroller does not send a Stop condition after the

first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller

can transmit up to 127 more data words. The EEPROM will respond with a zero after each data word received. The

microcontroller must terminate the page write sequence with a Stop condition (see Figure 9-2 on page 10) and the

internally timed write cycle will begin.

The lower seven bits of the data word address are internally incremented following the receipt of each data word. The

higher data word address bits are not incremented, retaining the memory page row location. When the word address,

internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more

than 128 data words are transmitted to the EEPROM, the data word address will roll-over, and the previous data will be

overwritten. The address roll over during write is from the last byte of the current page to the first byte of the same page.

Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,

Acknowledge Polling can be initiated. This involves sending a Start condition followed by the device address word. The

read/write select bit is representative of the operation desired. Only if the internal write cycle has completed will the

EEPROM respond with a zero, allowing the read or write sequence to continue.

Data Security: AT24C512C has a hardware data protection scheme that allows the user to write protect the entire

memory when the WP pin is at VCC.

Atmel AT24C512C [DATASHEET]

9

8720C–SEEPR–7/12

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