AT25640BN-SH-B 查看數據表（PDF） - Atmel Corporation

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AT25640BN-SH-B

SPI Serial EEPROMs 32K (4096 x 8) 64K (8192 x 8)

Atmel Corporation 

A write instruction requires the following sequence. After the CS line is pulled low to select the

device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15–A0)

and the data (D7–D0) to be programmed (see Table 2-6). Programming will start after the CS pin

is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time

immediately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be determined by initiating a read status register

(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle

has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25320B/640B is capable of a 32-byte page write operation. After each byte of data is

received, the five low-order address bits are internally incremented by one; the high-order bits of

the address will remain constant. If more than 32 bytes of data are transmitted, the address

counter will roll over and the previously written data will be overwritten. The AT25320B/640B is

automatically returned to the write disable state at the completion of a write cycle.

NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and

will return to the standby state, when CS is brought high. A new CS falling edge is required to

reinitiate the serial communication.

Table 2-6. Address Key

Address

AN

Don’t Care Bits

3. Timing Diagrams

Figure 3-1. Synchronous Data Timing (for Mode 0)

CS

SCK

VIH

VIL

tCSS

VIH

VIL

VIH

SI

VIL

tWH

tSU

tH

VALID IN

VOH

SO

VOL

HI-Z

AT25320B

A11–A0

A15–A12

tWL

AT25640B

A12–A0

A15–A13

tCS

tCSH

tV

tHO

tDIS

HI-Z

10 AT25320B/640B

8535B–SEEPR–7/08

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