AT29LV512-12JC 查看數據表（PDF） - Atmel Corporation

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AT29LV512-12JC

512K 64K x 8 3-volt Only CMOS Flash Memory

Atmel Corporation 

0177M–05/02

AT29LV512

Any attempt to write to the device without the 3-byte command sequence will start the

internal write timers. No data will be written to the device; however, for the duration of

tWC, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is per-

formed by applying a low pulse on the WE or CE input with CE or WE low (respectively)

and OE high. The address is latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or WE.

The 128 bytes of data must be loaded into each sector. Any byte that is not loaded dur-

ing the programming of its sector will be erased to read FFh. Once the bytes of a sector

are loaded into the device, they are simultaneously programmed during the internal pro-

gramming period. After the first data byte has been loaded into the device, successive

bytes are entered in the same manner. Each new byte to be programmed must have its

high-to-low transition on WE (or CE) within 150 µs of the low-to-high transition of WE (or

CE) of the preceding byte. If a high-to-low transition is not detected within 150 µs of the

last low-to-high transition, the load period will end and the internal programming period

will start. A7 to A15 specify the sector address. The sector address must be valid during

each high-to-low transition of WE (or CE). A0 to A6 specify the byte address within the

sector. The bytes may be loaded in any order; sequential loading is not required. Once a

programming operation has been initiated, and for the duration of tWC, a read operation

will effectively be a polling operation.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent

programs to the AT29LV512 in the following ways: (a) VCC sense – if VCC is below 1.8V

(typical), the program function is inhibited; (b) VCC power on delay – once VCC has

reached the VCC sense level, the device will automatically time out 10 ms (typical)

before programming; (c) Program inhibit – holding any one of OE low, CE high or WE

high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on

the WE or CE inputs will not initiate a program cycle.

INPUT LEVELS: While operating with a 3.3V ±10% power supply, the address inputs

and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely

affecting the operation of the device. The I/O lines can only be driven from 0 to 3.6 volts.

PRODUCT IDENTIFICATION: The product identification mode identifies the device

and manufacturer as Atmel. It may be accessed by hardware or software operation. The

hardware operation mode can be used by an external programmer to identify the correct

programming algorithm for the Atmel product. In addition, users may wish to use the

software product identification mode to identify the part (i.e., using the device code), and

have the system software use the appropriate sector size for program operations. In this

manner, the user can have a common board design for 256K to 4-megabit densities

and, with each density’s sector size in a memory map, have the system software apply

the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identifi-

cation. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT29LV512 features DATA polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte loaded will result

in the complement of the loaded data on I/O7. Once the program cycle has been com-

pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may

begin at any time during the program cycle.

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