AT49F002A 查看數據表（PDF） - Atmel Corporation

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AT49F002A

2-megabit (256K x 8) 5-volt Only Flash Memory

Atmel Corporation 

3. Block Diagram

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

AT49F002A(N)(T)

AT49F002A(N)

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

MAIN MEMORY

BLOCK 4

(64K BYTES)

MAIN MEMORY

BLOCK 3

(64K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

3FFFF

30000

2FFFF

20000

1FFFF

10000

0FFFF

08000

07FFF

06000

05FFF

04000

03FFF

00000

AT49F002A(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

BOOT BLOCK

(16K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 3

(64K BYTES)

MAIN MEMORY

BLOCK 4

(64K BYTES)

3FFFF

3C000

3BFFF

3A000

39FFF

38000

37FFF

30000

2FFFF

20000

1FFFF

10000

0FFFF

00000

4. Device Operation

4.1 Read

The AT49F002A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,

the data stored at the memory location determined by the address pins is asserted on the out-

puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention.

4.2 Command Sequences

When the device is first powered on, it will be reset to the read or standby mode depending upon

the state of the control line inputs. In order to perform other device functions, a series of com-

mand sequences are entered into the device. The command sequences are shown in the

Command Definitions table. The command sequences are written by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE or WE (except for the sixth cycle of the Sector Erase command), whichever

occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor

write timings are used. The address locations used in the command sequences are not affected

by entering the command sequences.

3

3354G–FLASH–3/05

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