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AT88SC1003 查看數據表(PDF) - Atmel Corporation

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AT88SC1003 Datasheet PDF : 30 Pages
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AT88SC1003
Table 3. Memory Zones (Continued)
Zone
Definition
Application Zone 3
AZ3 (512 bits)
AZ3 is intended to hold user application data. P3 (address 1024) controls write access and R3
(address 1025) controls read access within Zone 3. In Security Level 1, erasing AZ3 is accomplished
by performing an erase operation on any bit within AZ3 after verification of the security code (SV flag
= 1). This operation will erase the entire zone. In Security Level 2, erase operations are controlled by
both the SV flag and the erase key EZ3. See Table 9 on page 15 for specific details. There is no limit
to the number of erase operations performed in AZ3. In Security Level 1, write operations in AZ3 may
be performed on single bits after verification of the security code. In Security Level 2, the P3 bit must
also be set to “1” to allow single bit write operations. Read operations in Securtiy Levels 1 and 2 are
allowed if either R3 is set to “1” or the SV flag is set to “1” by validating the security code.
Application Zone 3
Erase Key EZ3
(1 bit)
The erase keys are passwords used to control erase operations within the application zones after the
issuer fuse has been blown (Security Level 2). The erase key password is written during
personalization (Security Level 1) after verification of the security code. EZ3 can not be changed after
the issuer fuse is blown. In Security Level 2, AZ3 can be erased only after both the security code and
the EZ3 password have been validated. Verification of EZ3 will set the internal flag E3 to “1”.
Application Zone 3
Erase Bit EB3
(1 bit)
Address location 1584 is designated as the erase bit for Application Zone 3. The erase protocol for an
AT88SC1003 in Security Mode 2 requires that the erase key (EZ3) be verified, then an erase
operation must be executed on the next bit following the erase key. This action will result in erasing the
entire zone.
Unused
(16 bits)
Address locations 1585–1599 are not functional in the AT88SC1003. If the address counter is
incremented beyond address 1599, the counter will roll over to address 0. The counter can also be
reset to “0” by executing a reset command.
Terminology
The following terms have specific definitions for the AT88SC1003.
• Erase
A program operation that results in an EEPROM data bit being set to a logic “1” state.
Outside the application zones, all erase operations are performed on 16-bit words. An
erase operation performed on any bit within a word will execute an erase of the entire
word. Inside an application zone, erase operations are controlled by the SV flag, EZ
passwords and the EC2EN fuse. These operations are defined in Table 9 on page 15.
• Write
A program operation that results in an EEPROM bit or word being set to a logic “0” state.
An unwritten bit is defined as erased, or set to a logic “1” state. Write operations in the
AT88SC1003 may be performed on individual bits after security code validation. In
Security Level 2, write operations also require that the P1, P2, or P3 bit within an appli-
cation zone is set to “1”.
• Program
An EEPROM function that activates internally timed, high-voltage circuitry and results in
a data bit or word being set to either a logic “0” or “1” state.
• Bit
A single data element set to either a logic “0” or “1” state. All bit addresses within the
application zones (AZ1, AZ2, AZ3) may be written individually.
• Byte
Eight consecutive data bits. A byte boundary will begin on an address that is evenly
divisible by 8. The AT88SC1003 has no capability for byte write operations.
7
2035B–SMEM–08/03

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