AT89C1051U 查看數據表（PDF） - Atmel Corporation
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AT89C1051U Datasheet PDF : 15 Pages
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AT89C1051U
Serial Port Timing: Shift Register Mode Test Conditions
VCC = 5.0V ± 20%; Load Capacitance = 80 pF
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
1.0
12tCLCL
700
10tCLCL-133
50
2tCLCL-117
0
0
700
10tCLCL-133
Shift Register Mode Timing Waveforms
Units
µs
ns
ns
ns
ns
AC Testing Input/Output Waveforms(1) Float Waveforms(1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a
logic 1 and 0.45V for a logic 0. Timing measurements
are made at VIH min. for a logic 1 and VIL max. for a
logic 0.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when 100 mV change from
the loaded VOH/VOL level occurs.
11
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