ATMEGA162L 查看數據表（PDF） - Atmel Corporation

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ATMEGA162L

8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash

Atmel Corporation 

can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on

page 216 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be

modified, causing the interrupted EEPROM access to fail. It is recommended to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CPU is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

Symbol

EEPROM write (from CPU)

Number of Calibrated RC

Oscillator Cycles(1)

8448

Typ Programming Time

8.5 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings

20 ATmega162/V

2513F–AVR–12/03

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