ATTINY20-XU 查看數據表（PDF） - Atmel Corporation
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ATTINY20-XU Datasheet PDF : 219 Pages
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6. Clock System
Figure 6-1 presents the principal clock systems and their distribution in ATtiny20. All of the clocks need not be active at a
given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different
sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 23. The
clock systems is detailed below.
Figure 6-1. Clock Distribution
ANALOG-TO-DIGITAL
CONVERTER
GENERAL
I/O MODULES
CPU
CORE
RAM
NVM
clk ADC
clk I/O
CLOCK CONTROL UNIT
clk CPU
clk NVM
SOURCE CLOCK
CLOCK
PRESCALER
RESET
LOGIC
WATCHDOG
CLOCK
WATCHDOG
TIMER
CLOCK
SWITCH
EXTERNAL
CLOCK
WATCHDOG
OSCILLATOR
CALIBRATED
OSCILLATOR
6.1 Clock Subsystems
The clock subsystems are detailed in the sections below.
6.1.1
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR Core. Examples of such modules
are the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU clock inhibits
the core from performing general operations and calculations.
6.1.2
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External
Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to
be detected even if the I/O clock is halted.
6.1.3
NVM clock - clkNVM
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously
with the CPU clock.
ATtiny20 [DATASHEET] 17
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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