ATTINY87-XU 查看數據表（PDF） - Atmel Corporation

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ATTINY87-XU

8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

Atmel Corporation 

2.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for

the chip. No internal clock division is used.

Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast access Register File concept. This is the basic pipelining

concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions

per cost, functions per clocks, and functions per power-unit.

Figure 2-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 2-5 shows the internal timing concept for the Register File. In a single clock cycle an

ALU operation using two register operands is executed, and the result is stored back to the

destination register.

Figure 2-5. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

2.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Inter-

rupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in Section 7. “Interrupts” on page 59.

The list also determines the priority levels of the different interrupts. The lower the address the

higher is the priority level. RESET has the highest priority, and next is INT0 – the External

Interrupt Request 0.

12 ATtiny87/ATtiny167

8265A–AVR–08/10

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