AV3168 查看數據表（PDF） - Unspecified

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AV3168

Video Encoder

Unspecified 

AV3168/69

VIDEO TIMING GENERATION

The video encoder can operate as a master or a slave in the timing generation. In the master mode, the video

encoder outputs SYNC signals. In the slave mode, the internal timing is lock to the external SYNC signals.

MASTER MODE

If the MSTR pin is high, the video encoder operates in the master mode. It uses the internal counters to generate

the video timing and outputs HSYN and VSYN. The HSYNs are asserted for 64 pixel times. The negative transition

of the HSYNs occur in the Cb slot.

The VSYNs are asserted for 3 line times for NTSC and 2.5 for PAL. The co-incident negative transitions of HSYN

and VSYN indicate the beginning of an odd field. The negative transition of the VSYN while the HSYN is high

indicates the beginning of an even field.

SLAVE MODE

In the slave mode operation, the decoder automatically detects the input format and locks the internal timing

counters to the external synchronization signals. It support 2 types of synch inputs: (a) HSYN / VSYNC, or (b)

CCIR656 EAV data.

If EAV is present, the video encoder synchronized to the EAV packets according to CCIR656 specifications to

generate the video timing. HSYN and VSYN signals are ignored.

If EAV is not present, the Video Encoder uses the signals presented on HSYN and VSYN for line and field counter

increment. If register CR0[3] is low the encoder assumes the negative transition of the HSYN should be co-incited

with the Cb0 datum. If CR0[3] is high it assume the transition co-incited with Y0 datum.

NTSC VERTICAL INTERVAL TIMING

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524 525

1

2

3

4

5

6

7

8

9

10 - 20

VSYN

Field One

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262 263 264 265 266 267 268 269 270 271 272

273 - 280

VSYN

Field Two

9-24

January 4, 2001

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