AZ100ELT23TR1(2012) 查看數據表（PDF） - AZ Microtek
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AZ100ELT23TR1 Datasheet PDF : 6 Pages
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AZ100ELT23
Dual Differential PECL to
CMOS/TTL Translator
DESCRIPTION
The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator.
Because PECL (Positive ECL) levels are used, only VCC and ground are
required. The small outline 8-lead packaging and the low skew, dual gate
design of the AZ100ELT23 makes it ideal for applications that require the
translation of a clock and a data signal.
The AZ100ELT23 is a direct replacement for the ON Semi MC100ELT23
www.azmicrotek.com
FEATURES
• 3.5ns typical propagation
delay
• <500ps typical output to
output skew
• Differential PECL inputs
• Flow through pinouts
• CMOS/TTL outputs
BLOCK DIAGRAM
APPLICATIONS
• LVPECL to LVCMOS/LVTTL
translations
• PECL to CMOS/TTL
translations
PACKAGE AVAILABILITY
• SOIC8
o Green/RoHS/Pb-Free
• MSOP8
o Green/RoHS/Pb-Free
Order Number
Package
Marking
AZ100ELT23DG1
SOIC8
HT23G2
AZ100ELT23T+1
MSOP8
HT23+2
1 Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in
2 See www.azmicrotek.com for date code format
www.azmicrotek.com
+1-480-962-5881
Request a Sample
1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0
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