VSC7960W 查看數據表（PDF） - Vitesse Semiconductor

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VSC7960W

3.125Gb/s CML Limiting Amplifier with LOS Detect and Laser Driver with Automatic Power Control

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7960

3.125Gb/s CML Limiting Amplifier with LOS Detect

and Laser Driver with Automatic Power Control

Figure 3: Laser Driver Block Diagram

VCC

DATA+

DATA-

ENABLE

DISABLE

MUX

APC

MODSET

BIASMAX

CAPC

OUT+

CD

OUT-

CF

RF

VCC

BIAS

VCC

MODMON

VCC

BIASMON

FAIL

APCSET_MD

1nF

Limiting Amplifier Squelch

Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to

TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not

asserted, the outputs will not be squelched.

Limiting Amplifier Loss of Signal (LOS) Detect

This features utilizes an rms power detector with programmable LOS indicator to provide two outputs, LOS

and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and LOS,

change state. See Loss-of-Signal Specifications table (Table 6) for setting the resistor value between TH and

ground. The Loss of Signal Truth Table (Table 7) clarifies how LOS and SQUELCH interact.

Limiting Amplifier Offset Correction

This feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not cause

the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-

frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low

frequency cut-off is 2MHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is

lowered to approximately 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2

open. For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor

between CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low

frequency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:

fOC = 43 / [2π * 35k (CZ + 100pF)]

= 196* 10-6 / (CZ + 100pF)

= 196* 10-6 / (0.1µF + 100pF)

= 1.96kHz

G52359-0, Rev 2.1

5/01/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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