VSC7962 查看數據表（PDF） - Vitesse Semiconductor

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VSC7962

3.125Gb/s PECL Limiting Amplifier with LOS Detect and Laser Driver with Automatic Power Control

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

3.125Gb/s PECL Limiting Amplifier with LOS Detect

and Laser Driver with Automatic Power Control

Advance Product Information

VSC7962

20Ω resistor should be placed in series with the laser. For optimal performance, a bypass capacitor should be

placed close to the laser anode.

A “snubber network” consisting of a capacitor CF and resistor RF should be placed at the laser output to

minimize reflections from the laser (see Block Diagram, page 1). Suggested values for these components are

80Ω and 2pF, respectively. However, these values should be adjusted until a suitable optical output waveform is

obtained.

Reducing Pattern-Dependent Jitter

Three design values significantly affect pattern-dependent jitter: the capacitor at CAPC, the pull-up induc-

tor at the output (LP), and the AC-coupling capacitor at the output (CD). As previously stated, the recommended

value for the capacitor at CAPC is 0.1µF. This results in a 10kHz loop bandwidth which makes the pattern-

dependent jitter from the APC loop negligible.

For 2.5Gb/s data rates, the recommended value for CD is 0.056µF. The time constant at the output is domi-

nated by LP. The variation in the peak voltage should be less that 12% of the average voltage over the maximum

consecutive identical digit (CID) period. The following equation approximates this time constant for a CID

period, t, of 100UI = 40ns:

τLP = -t / ln(1-12%) = 7.8t = LP / 25Ω

Therefore, the inductor LP should be a 7.8µH SMD ferrite bead inductor for this case.

Input/Output Considerations

Although the VSC7962 laser driver is PECL-compatible, this is not required to drive the device. The inputs

must only meet the common-mode voltage and differential voltage swing specifications.

Laser Driver Power Consumption

The following equation provides the device supply current (IS) in terms of quiescent current (IQ), modula-

tion current (IMOD), and bias current (IBIAS):

IS = IQ + 0.47 * IMOD + 0.15 * IBIAS

For 3.3V operation, IQ is 15mA.

This equation may be used to determine the estimated power dissipation:

PDIS = VCC * IS

For example, the device operated at 3.3V with a 30mA modulation current and a 10mA bias current would

have a supply current of:

IS = 15mA + 0.47 * 30mA + 0.15 * 10mA = 31mA

This corresponds to a power dissipation of 3.3V * 31mA = 102mW.

Page 16

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52361-0, Rev 2.1

05/01/01

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