(9)MOSFET selection
VCC
VDS
IL
Vo
VGSM1
VGSM2
VDS
Fig-33
(10)Schottky barrier diode selection
VCC
Vo
VR
Fig-34
FET uses Nch MOS
・VDS>Vcc
・VGSM1>BOOT-SW interval voltage
・VGSM2>VREG5
・Allowable current>voltage current + ripple current
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
・ Reverse voltage VR>Vcc
・ Allowable current>voltage current + ripple current
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for highest
efficiency
・ The shoot-through may happen when the input parasitic
capacitance of FET is extremely big or the Duty ratio is less
than or equal to 10%. Less than or equal to 1000pF input
parasitic capacitance is recommended. Please confirm
operation on the actual application since this character is
affected by PCB layout and components.
(11)Sequence function
●Circuit diagram
VCC VREG5
VREG5
Vo1
OUTH1 BOOT1 VCC BOOT2 OUTH2
SW1
OUTL1
DGND1
SW2
OUTL2
DGND2
FB1
COMP1
FB2
COMP2
SS1
SS2
DET2
DET1
STB EN1 EN2 GND
Fig-35
●Timing chart
With EN1, 2 at ”H” level, when EN1 goes ”L”,
Vo1 turns OFF, but Vo2 output continues.
When EN1 stays ”H” and EN2 returns to ”H”, DET1 is in
open state; thus SS2 is asserted, and Vo2 output starts.
If Vo2 is 76% of the voltage setting or higher, DET2 goes
open and SS1 is asserted, starting Vo1 output.
Vo2
EN1
EN2
DET2
SS1
FB1
0.61V
Vo1
DET1
SS2
FB2
over 76%
0.56V
0.61V
0.56V
Vo2
under 70%
over 70%
over 76%
With EN1,2 at “H” level, if
Vo1 starts at 76% or more of
voltage setting, DET goes
open and SS1 is asserted,
starting Vo2 output.
A With EN2 set ”L”, if Vo2
A
goes below 70% the voltage
setting, DET2 shorts and SS1
is asserted, turning Vo1 OFF
Same as “A” at left
Fig-36
12/28