NG80960JA/JF-16 查看數據表（PDF） - Intel

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NG80960JA/JF-16

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

Intel 

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 3.

Pin Description — External Bus Signals (Sheet 2 of 3)

NAME

TYPE

DESCRIPTION

BE3:0

WIDTH/

HLTD1:0

D/C

W/R

DT/R

DEN

O

R(1)

H(Z)

P(1)

O

R(0)

H(Z)

P(1)

O

R(X)

H(Z)

P(Q)

O

R(0)

H(Z)

P(Q)

O

R(0)

H(Z)

P(Q)

O

R(1)

H(Z)

P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate in the

current bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

32-bit bus:

BE3 enables data on AD31:24

BE2 enables data on AD23:16

BE1 enables data on AD15:8

BE0 enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enable (enables data on AD15:8)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3 is not used (state is high)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during Ta.

Since unaligned bus requests are split into separate bus transactions, these signals

do not toggle during a burst. They remain active through the last Td cycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in

conjunction with A3:2 described above.

WIDTH/HALTED signals denote the physical memory attributes for a bus

transaction:

WIDTH/HLTD1 WIDTH/HLTD0

0

0

8 Bits Wide

0

1

16 Bits Wide

1

0

32 Bits Wide

1

1

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in

response to a HOLD request, regardless of prior operating state.

DATA/CODE indicates that a bus access is a data access (1) or an instruction

access (0). D/C has the same timing as W/R.

0 = instruction access

1 = data access

WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or

read (0). It is latched on-chip and remains valid during Td cycles.

0 = read

1 = write

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta

and Tw/Td cycles for a write. DT/R never changes state when DEN is asserted.

0 = receive

1 = transmit

DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted

at the start of the first data cycle in a bus access and deasserted at the end of the

last data cycle. DEN is used with DT/R to provide control for data transceivers

connected to the data bus.

0 = data cycle

1 = not data cycle

18

Advance Information Datasheet

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