SAA7201H/C3 查看數據表（PDF） - Philips Electronics

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SAA7201H/C3

3.3 V, integrated MPEG2 AVG decoder / QFP160 Package

Philips Electronics 

Philips Semiconductors

Integrated MPEG2 AVG decoder

Objective specification

SAA7201

Audio decoding will be performed at a clock locked to the

video decoding clock and only the output interface is

running on the audio oversampling clock.

The audio decoder unit performs the decoding of the

selected MPEG audio stream in a range from 8 up to

448 kbit/s in a fixed or variable bit rate format. Decoding is

restricted to 2 channel, layer I, II MPEG audio at sampling

frequency of 48.0, 44.1, 32.0, 24.0, 22.05 or 16.0 kHz.

The audio decoder support the stop, mute, and skip

function to support insertion

Apart from basic MPEG processing the audio decoder

core contain also:

• Support for: stop, mute and skip function.

• Fully parameterized dynamic range compression unit to

decrease the dynamic range of the output signal on

audio frame basis. Depending on the power level a

programmable amplification and offset may be applied.

• Fully programmable base band audio processing unit to

control the gain in both output channels independently

and/or to mix both channels.

• MPEG de-emphasis filtering on the output data, thus

avoiding the need of external analog de-emphasis filter

circuitry.

• Storage buffer for the last 54 bytes of each audio frame.

The CPU can retrieve eventual ancillary data from this

buffer.

The output of the audio decoder unit can be mixed with

square waveform audio signals which are generated by a

beep generator. Programmable parameters for the beep

generator are amplitude, frequency and duration.

The audio output interface module produces stereo base

band output samples on two different outputs at the same

time:

• Serial digital audio in I2S-bus or in Japanese format in

16, 18, 20 or 22-bit

• SPDIF (Sony/Philips Digital Interface).

Any of the two outputs may be enabled or set to high

impedance mode. The I2S-bus format with 18-bit sample

precision is shown in Fig.6.

The difference between I2S-bus and the Japanese format

is that I2S-bus is MSB aligned whereas the Japanese

format is LSB aligned.

The 1-bit serial interface SPDIF contains 64-bit per audio

sample period. Complete frames must be transmitted at

the audio sample rate. Not only left/right information but

also validity flags, channel status, user data and parity

information is contained in an SPDIF frame (see Chapter

“References”).

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MGD326

1997 Jan 29

Fig.6 I2S-bus format with 18-bit sample precision.

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