SAA7201H/C2 查看數據表（PDF） - Philips Electronics

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SAA7201H/C2

3.3 V, integrated MPEG2 AVG decoder / QFP160 Package

Philips Electronics 

Philips Semiconductors

Integrated MPEG2 AVG decoder

Objective specification

SAA7201

• The chroma up-conversion unit converts the MPEG

4 : 2 : 0 format into the at the output required

4 : 2 : 2 format. This vertical up-conversion is performed

by a simple 8-phase interpolation between two adjacent

lines.

• The mixer units combine MPEG video with graphics and

cursor information in two steps. In a first step the MPEG

decoded information is mixed with graphical information.

Mixing can be done at pixel basis in 64 steps and is

controlled by the internally implemented colour look up

table. In a second step, the video plus graphics can be

mixed in 4 steps with the internally generated cursor.

• The output formatting unit performs two main tasks, i.e.

synchronization and formatting. Synchronization is

characterized by three signals being horizontal (H),

vertical (V) and field parity (FP), all having

programmable length and polarity.

Since the decoder can operate in master or slave mode,

the synchronization signals can be generated by the

decoder or should be delivered by an external device.

In both cases the length and polarity should be

programmed internally.

The video output samples are supplied in a multiplexed

YUV format to the output. Next to this byte wide YUV

stream, which can directly be supplied to most

commercially available composite video encoder ICs,

three additional signals are delivered at the output.

HREF indicates all active samples; CREF can flag any

combination of pixels: U, V, Yodd and/or Yeven; GRPH

flags all the pixels inside a graphical box.

Additionally the full YUV bus can be set to a HIGH

impedance state under control of the signal YUV_ENA.

This might be useful for multiplexing the MPEG decoder

output with any other signal source on static basis.

handbook, fullCpLagKewidth

YUV

'128'

HREF

CREF

(example)

GRPH

'16'

U0

Y0

V0

Fig.12 Timing diagram of graphics information output.

Y2

MGD332

1997 Jan 29

19

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