AS7C3256PFS16A-3.8 查看數據表（PDF） - Alliance Semiconductor
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AS7C3256PFS16A-3.8 Datasheet PDF : 11 Pages
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Advance information
AS7C3256PFS16A
AS7C3256PFS18A
®
Signal
I/O Properties
Description
CLK
I CLOCK
Clock. All inputs except OE are synchronous to this clock.
A0–A17 I SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b,c,d] I/O SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more
information.
CE1, CE2 I SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE1 and ADSP are active.
ADSP
I SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSC
I SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV
I SYNC
Burst advance. Asserted LOW to continue burst read/write.
GWE
I SYNC
Global write enable. Asserted LOW to write all 36 bits. When HIGH, BWE and BW[a:b]
control write enable.
BWE
I SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:b] inputs.
BW[a,b] I SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a:b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:b] are inactive, the cycle is a read cycle.
OE
I ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
synchronously enabled.
LBO
I
STATIC default = HIGH
Count mode. When driven HIGH, count sequence follows Intel XOR convention. When
driven LOW, count sequence follows linear convention. This signal is internally pulled HIGH.
FT
I
STATIC default = HIGH
Flow-through mode.When LOW, enables single register flow-through mode. Connect to
VDD if unused or for pipelined operation. This signal is internally pulled HIGH
ZZ
I ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–
1.4
W
DC output current
Storage temperature (plastic)
Temperature under bias
IOUT
–
Tstg
–65
Tbias
–65
50
mA
+150
oC
+150
oC
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reli-
ability.
DID 11-20027-A. 6/8/00
ALLIANCE SEMICONDUCTOR
3
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