AS4LC4M16S0-10FTC 查看數據表（PDF） - Alliance Semiconductor

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AS4LC4M16S0-10FTC

3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Alliance Semiconductor 

AS4LC8M8S0

AS4LC4M16S0

®

Device operation (continued)

Command

Pin Settings

Description

Burst stop

CS = WE = low; RAS = Use burst stop to terminate burst operation. This command may be used

CAS = high

to terminate all legal burst lengths.

Bank precharge

The Bank Precharge command precharges the bank specified by BA0 and

CS = A10 = RAS = WE =

low; CAS = high; A11 =

bank select; A0~A9 =

don’t care

BA1. The precharged bank is switched from active to idle state and is

ready to be activated again. Assert the precharge command after

tRAS(min) of the bank activate command in the specified bank. The

precharge operation requires a time of tRP(min) to complete.

CS = RAS = WE = low;

Precharge all

CAS = A10 = high; The Precharge All command precharges all four banks simultaneously.

BA0~BA1 = bank select; All four banks are switched to the idle state on precharge completion.

A0~A9 = don’t care

CS = CAS = WE (write) = During auto precharge, the SDRAM adjusts internal timing to satisfy

Auto precharge

low; RAS = WE (read) = tRAS(min) and tRP for the programmed CAS latency and burst length.

A10 = high; BA0~BA1 = Couple the auto precharge with a burst read/write operation by

bank select; A0~A9 = asserting A10 to a high state at the same time the burst read/write

column address; (A9 = commands are issued. At auto precharge completion, the specified bank

don’t care for 2M×8; is switched from active to idle state. Note that no new commands to the

A8,A9 = don’t care for bank can be issued until the specified bank achieves the idle state. Auto

1M×16)

precharge doesn’t work with full-page burst.

Clock suspend/power

down mode entry

CKE = low

When CKE is low, the internal clock is frozen or suspended from the

next clock cycle and the state of the output and burst address are frozen.

If all banks are idle and CKE goes low, the SDRAM enters power down

mode at the next clock cycle. When in power down mode, no input

commands are acknowledged as long as CKE remains low. To exit power

down mode, raise CKE high before the rising edge of CLK.

Clock suspend/power

down mode exit

CKE = high

Resume internal clock operation by asserting CKE high before the rising

edge of CLK. Subsequent commands can be issued one clock cycle after

the end of the Exit command.

SDRAM storage cells must be refreshed every 64ms to maintain data

integrity. Use the Auto Refresh command to refresh all rows in all banks

of the SDRAM. The row address is provided by an internal counter

Auto refresh

CS = RAS = CAS = low;

WE = CKE = high;

A0~A11 = don’t care

which increments automatically. Auto refresh can only be asserted when

all four banks are idle and the device is not in the power down mode.

The time required to complete the auto refresh operation is tRC(min).

Use NOPs in the interim until the auto refresh operation is complete.

This is the most common refresh mode. It is typically performed once

every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All

four banks will be in the idle state after this operation.

Self refresh is another mode for refreshing SDRAM cells. In this mode,

refresh address and timing are provided internally. Self refresh entry is

allowed only when all four banks are idle. The internal clock and all

CS = RAS = CAS = CKE = input buffers with the exception of CKE are disabled in this mode. Exit

Self refresh

low; WE = high; A0~A11 self refresh by restarting the external clock and then asserting CKE high.

= don’t care

NOP’s must follow for a time of tRC(min) for the SDRAM to reach the

idle state where normal operation is allowed. If burst auto refresh is used

in normal operation, burst 4096 auto refresh cycles immediately after

exiting self refresh.

7/5/00

ALLIANCE SEMICONDUCTOR

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