M48T129V(2005) 查看數據表（PDF） - STMicroelectronics

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M48T129V
(Rev.:2005)

5.0 or 3.3V, 1 Mbit (128 Kbit x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T129Y, M48T129V

Power-on Reset

The M48T129Y/V continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and remains low on

power-up for tREC after VCC passes VPFD (max).

The RST pin is an open drain output and an appro-

priate pull-up resistor to VCC should be chosen to

control the rise time.

Battery Low Warning

The M48T129Y/V automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

Register 1FFF0h, will be asserted if the battery

voltage is found to be less than approximately

2.5V.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied.

The M48T129Y/V only monitors the battery when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

Initial Power-on Defaults

Upon application of power to the device, the fol-

lowing register bits are set to a '0' state: WDS,

BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.

VCC Noise And Negative Going Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor value of 0.1µF (see Figure 14.) is

recommended in order to provide the needed fil-

tering.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate neg-

ative voltage spikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, ST recommends connecting

a schottky diode from VCC to VSS (cathode con-

nected to VCC, anode to VSS). (Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface-mount).

Figure 14. Supply Voltage Protection

VCC

0.1µF

VCC

DEVICE

VSS

AI02169

19/30

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